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AssigneeAgere Systems Guardian Corp.
InventorsYoung-Kai Chen, Alfred Yi Cho, William Scott Hobson, Minghwei Hong, Jenn-Ming Kuo, Jueinai Raynien Kwo, Donald Winslow Murphy, Fan Ren
Estimating the term…
Disclosed are a method of making GaAs-based enhancement-type MOS-FETs, and articles (e.g., GaAs-based ICs) that comprise such a MOS-FET. The MOS-FETs are planar devices, without etched recess or epitaxial re-growth, with gate oxide that is primarily Ga2O3, and with low midgap interface state density (e.g., at most 1×1011 cm−2 eV−1 at 20° C.). The method involves ion implantation, implant activation in an As-containing atmosphere, surface reconstruction, and in situ deposition of the gate oxide. In preferred embodiments, no processing step subsequent to gate oxide formation is carried out above 300° C. in air, or above about 700° C. in UHV. The method makes possible fabrication of planar enhancement-type MOS-FETs having excellent characteristics, and also makes possible fabrication of complementary MOS-FETs, as well as ICs comprising MOS-FETs and MES-FETs. The method includes deposition of gate oxide of overall composition GaxAyOz, where Ga substantially is in the 3+ oxidation state, A is one or more electropositive stabilizer element adapted for stabilizing Ga in the 3+ oxidation state, x is greater than or equal to zero, z is selected to satisfy the requirement that both Ga and A are substantially fully oxidized, and y/(x+y) is greater than 0.1.
A method of making a GaAs-based integrated circuit comprising at least one planar metal-oxide-semiconductor field effect transistor (“MOS-FET”), the method comprising
Dependencies are inferred from the claim text.
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Characterised by the insulator, e.g. by the gate insulator: comprising metallic compounds, e.g. metal oxides or metal silicates
Characterised by the coating material: oxides
Manufacture or treatment: of FETs having insulated gates [IGFET]
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
Term ended 23 Mar 2014 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention pertains to methods of making articles that comprise an oxide layer on a GaAs-based semiconductor body, typically GaAs-based field effect transistors (FETs).
GaAs-based transistors and circuits are used in, for instance, wireless communication apparatus, due inter alia to the relatively high electron mobility in GaAs, the availability of semi-insulating GaAs substrates, and the relative simplicity of the manufacturing processes.
Si-based metal oxide semiconductor (MOS) field effect transistors (FETs) are known, and are widely used. Among the advantages of Si-based MOS-FETs are simplicity, low power and low cost. The most common Si-based MOS-FET is the enhancement-type MOS-FET, which is “normally off” with zero gate voltage.
FIG. 1 shows exemplary data on vacuum pressure vs. time during the relevant portion of the process of forming an oxide layer on (100) GaAs;
FIGS. 2 and 3 show photoluminescence data that illustrate, respectively, the thermochemical and photochemical stability of GaAs/oxide interfaces;
FIG. 4 presents exemplary data on capacitance vs. gate voltage of a MOS structure;
Like or analogous features generally are designated by the same numeral in different figures. The figures are not to scale.
We have found that, by providing a substantially atomically clean and substantially atomically ordered (typically (100)-oriented) surface of a GaAs-based semiconductor body, and by appropriately limiting exposure of the surface to contaminants prior to completion of the first monolayer of oxide dielectric material on the surface, GaAs-based semiconductor/oxide layer structures having greatly improved interface characteristics can be produced. According to our present understanding, the exposure of the surface to impurities desirably is such that, at tm, impurity coverage of the surface is less than 1% of a monolayer, exemplarily such that the exposure of the surface to impurities is at most 100 Langmuirs (preferably less than 50 or 10 Langmuir. Our measurements to date have not revealed a significant difference in interface quality between structures that had exposures of 100 Langmuirs and 10 Langmuirs, respectively, although the existence of a difference cannot be ruled out. However, we expect that exposure substantially in excess of 100 Langmuirs will result in reduced quality interfaces.
Although in principle any apparatus that can provide the substantially atomically clean surface at t=tc, and the required low exposure during the time from tc to tm is potentially suitable for the practice of the invention, in practice the apparatus typically will comprise one or more UHV chambers. In the case of multichamber apparatus, two chambers will generally be linked together by a transfer module which facilitates transfer of the semiconductor body from one chamber to the other without exposure of the body to the ambient atmosphere. Typically the transfer is under UHV conditions. Such apparatus is known. See, for instance, M. Hong et al., J. Electronic Materials, Vol. 23, 625 (1994).