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US 6,269,034 B1Granted
Semiconductor memory having a redundancy judgment circuit
AssigneeNEC Corporation
InventorMasahiro Shibuya
Life of this patent
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Abstract
In a semiconductor memory having a redundancy circuit, when a defective cell is replaced with a redundancy cell, activation of a normal word line is retarded until it is judged whichever of a redundancy word line and a normal word line should be activated. The semiconductor memory has address pre-decoders enabling selection and driving of a normal word line, and a redundancy control circuit for judging whether a redundancy word line should be activated. The address pre-decoders and redundancy control circuit are controlled mutually independently. Irrespective of whether a redundancy word line is used, a normal word line can be controlled earlier. Consequently, the action of the whole semiconductor memory can be speeded up.
Claims21
A semiconductor memory device, comprising:
- a plurality of normal memory cells;
- a plurality of redundancy memory cells;
- a plurality of normal word lines connected to said normal memory cells;
- a plurality of redundancy word lines connected to said redundancy memory cells and including at least a first redundancy word line;
- a normal word decoder for selecting and driving one of said normal word lines corresponding to an external address signal provided in response to a first clock signal;
- a redundancy word decoder for driving said first redundancy word lines;
- address judging means for judging whether said external address signal corresponds to the address of a defective normal memory cell;
- and
- a redundancy control circuit having inputs connected to said address judging means and having outputs connected to said normal word decoder and said redundancy word decoder,
- wherein said redundancy control circuit activates said redundancy word decoder and inactivates said normal word decoder in response to a second clock signal which is different from said first clock signal, if said external address signal corresponds to the address of a defective normal memory cell.
7 more elements
A semiconductor memory device, comprising:
- a plurality of normal word lines connected to normal memory cells;
- a plurality of redundancy word lines connected to redundancy memory cells;
- a row address buffer supplied with external address signals;
- an address judging circuit connected to said row address buffer;
- a plurality of address pre-decoders connected to said row address buffer, and provided with a row address signal in response to a first clock signal;
- a redundancy control circuit connected to said address judging circuit, and provided with output signals of said address judging circuit in response to a second clock signal;
- a redundancy word decoder connected to said redundancy control circuit, and driving one of said redundancy word lines in response to a redundancy word line enabling signal generated from said redundancy control circuit;
- and
- a normal word decoder connected to said address pre-decoders, and driving one of said normal word lines in response to a normal word line enabling signal generated from said redundancy control circuit,
- wherein said first clock signal is activated earlier than said second clock signal, when said row address signals corresponds to a defective memory cell in said normal memory cell, said redundancy control circuit sets said redundancy word decoder activating and said normal word decoder inactivating.
7 more elements
A semiconductor memory device, comprising:
- a plurality of normal word lines connected to normal memory cells;
- a plurality of redundancy word lines connected to redundancy memory cells;
- a plurality of row address buffers supplied with each of external address signals;
- an address judging circuit connected to said row address buffers;
- a plurality of address pre-decoders connected to each of said row address buffers, and provided with each of row address signals in response to a first clock signal;
- a redundancy control circuit connected to said address judging circuit, and provided with output signals of said address judging circuit in response to a second clock signal;
- a redundancy word decoder connected to said redundancy control circuit, and driving one of said redundancy word lines in response to a redundancy word line enabling signal generated from said redundancy control circuit;
- a cell plate selection circuit, connected to said address pre-decoders and said redundancy control circuit, supplied with a sense amplifier enabling signal and generating a sense amplifier driving signal;
- and
- a normal word decoder connected to said address pre-decoders,
- wherein said first clock signal is activated earlier than said second clock signal.
8 more elements
A semiconductor memory device, comprising:
- an address judging circuit;
- a plurality of address pre-decoders provided with each of row address signals in response to a first clock signal;
- a redundancy control circuit connected to said address judging circuit, and provided with output signals of said address judging circuit in response to a second clock signal;
- a redundancy word decoder connected to said redundancy control circuit, and driving a redundancy word line in response to a redundancy word line enabling signal generated from said redundancy control circuit;
- and
- a cell plate selection circuit connected to said address pre-decoders and said redundancy control circuit, supplied with a sense amplifier enabling signal and generating a sense amplifier driving signal.
3 more elements
Dependencies are inferred from the claim text.