Self-test for charge redistribution analog-to-digital converter

A method of testing a charge redistribution analog-to-digital converter with on-board self-test capability, comprising the steps of, on a single semiconductor chip:

• providing a binary weighted capacitor array having a plurality of capacitors, each capacitor having a pair of plates, one plate of each of the capacitors being electrically connected to a common node;
• providing a comparator having one input electrically connected to the common node and having an output;
• providing successive approximation logic circuitry electrically connected to the comparator output and the array for selectively connecting the capacitors to preselected voltages in an analog-to-digital conversion cycle comprising sample, hold and charge redistribution phases;
• providing logic circuitry for control of the other plate of each of said capacitors;
• commonly connecting said other plate of each of said capacitors under control of said logic circuitry to an analog input signal during the sample phase while connecting said common node to an internally generated common mode voltage to charge said capacitors in accordance with a sample signal;
• then commonly connecting the other plate to a low reference voltage under control of said logic circuitry during the hold phase while concurrently disconnecting said common node from said common mode voltage;
• then successively connecting the other plate to the other of the high or low reference voltage during the charge redistribution phase under control of said logic circuitry;
• providing a test data generator for generating a test pattern sequence in the form of a digital signal;
• and
• electrically connecting the test data generator to the logic circuitry for selectively controlling the logic circuitry to connect said other plate of each of the capacitors to one or the other of the high or low reference voltage to charge the capacitors according to said predetermined test pattern sequence during the sample phase of a test mode.

A method of testing a charge redistribution analog-to-digital converter;

• the converter having a binary weighted capacitor array with a plurality of capacitors, each capacitor having a pair of plates, one plate of each capacitor being electrically connected to a common node, a comparator having one input electrically connected to the common node and having an output, and successive approximation logic circuitry electrically connected to the comparator output and the array including a plurality of switches respectively associated with the capacitors for selectively connecting the capacitor to a high reference voltage, low reference voltage or analog input signal voltage to develop a digital output according to the settings of the switches in a successive charge redistribution conversion process comprsing sample, hold and charge redistribution phases;
• the test method comprising the steps of, on a single semiconductor chip:
• providing a test generator for providing a digital test pattern binary data bit sequence;
• in the sample phase, setting the switches according to respective corresponding bits in the sequence of the digital test pattern to connect said other plate of each capacitor to one or the other of the high or low reference voltage to charge the capacitors according to the switch settings established by the test pattern;
• in the hold phase, then setting the switches to commonly connect said other plate of each capacitor to the same one of the high or low reference voltage;
• in the redistribution phase, then successively resetting the switches to connect said other plate to the same other of the high or low reference voltage;
• developing an output digital binary data bit sequence based on the settings of the switches at the completion of the charge redistribution phase;
• and
• comparing the output digital binary data bit sequence with the digital test pattern binary data bit sequence.