US 6,266,799 B1 · Multi-phase data/clock recovery circuitry and methods for implementing same

Abstract

Disclosed is a data/clock recovery system for use in a high speed networking transceiver units. The data/clock recovery system includes a four phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the four phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. A counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, such that the shifting is configured to synchronize the clock and the data input waveform. A decoder that receives control signals from the counter, such that the decoder generates a selection signal. The data/clock recovery system further including a multiplexer for selecting four predetermined clock phases in response to the selection signal generated by the decoder. Preferably, the four predetermined clock phases are continually shifted by the counter if the clock and the data input waveform are not synchronized.

Claims8

Dependent claims

A method for implementing a data/clock recovery system in a network device receiver, the network device receiver being configured to receive a serial data stream, comprising:

producing a plurality of clock phases for every two bits of the serial data stream;
selecting four clock phases from the plurality of clock phases, the four clock phases having a predetermined separation;
analyzing the serial data stream that corresponds to the selected four clock phases to determine whether a new four clock phases should be selected from the plurality of clock phases;
and
selecting the new four clock phases when the analyzing indicates that the selected four clock phases and the serial data stream are not synchronized, the new four clock phases are selected to prevent the selected four clock phases from leading or lagging the serial data stream.
wherein the serial data stream is continually analyzed for each of the every two bits of the serial data stream and the new four clock phases are only selected when the analyzing indicates that the selected four clock phases and the serial data stream are not synchronized.

3 more elements

Dependencies are inferred from the claim text.

Multi-phase data/clock recovery circuitry and methods for implementing same

Life of this patent

Multi-phase data/clock recovery circuitry and methods for implementing same

Life of this patent

Abstract

Claims8