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US 6,265,898 B1Granted
Current mode logic gates for low-voltage high speed applications
AssigneeTexas Instruments Incorporated
InventorAbdellatif Bellaouar
Life of this patent
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Abstract
A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.
Claims4
A prescaler circuit, comprising:
- an input buffer coupling input signals to clock and inverted clock signal inputs of first, second and third flip-flops;
- a first input of said first flip-flop coupled to a first output of said second flip-flop;
- a second input of said first flip-flop coupled to a first output of said third flip-flop;
- a first output of said first flip-flop coupled to a first input of said second flip-flop and to a first clock input of a fourth flip-flop;
- a second output of said first flip-flop coupled to a second input of said second flip-flop and to a second clock input of said fourth flip-flop;
- a second output of said second flip-flop coupled to a first input of said third flip-flop;
- a first output of said fourth flip-flop coupled to a second input of said third flip-flop and to a first clock input of a fifth flip-flop;
- a second output of said fourth flip-flop coupled to a second clock input of said fifth flip-flop;
- a third input of said third flip-flop coupled to the output of a logic gate;
- a first input of said logic gate coupled to receive a select signal;
- a first output of said fifth flip-flop coupled to a first clock input of a sixth flip-flop and to a second input of said logic gate;
- a second output of said fifth flip-flop coupled to a second clock input of said sixth flip-flop;
- a third input of said logic gate coupled to a first output of said sixth flip-flop.
10 more elements
Dependencies are inferred from the claim text.