Hardware and software co-simulation including simulating the cache of a target processor

A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, first and second target processors, and accompanying first and second user programs to be executed on each of the target processors, at least the first target processor having a cache, the design system comprising:

• a first processor simulator using software executing on the host computer system for simulating execution of the first user program on the first target processor, the software including an analyzed version of the first user program;
• a second processor simulator using software executing on the host computer system for simulating execution of the second user program on the second target processor, the software including an analyzed version of the second user program;
• a hardware simulator to simulate the target digital circuitry using software executing on the host computer system;
• and
• an interface mechanism that couples the hardware simulator with the first and second processor simulators, including controlling communication between the first and second processor simulators and the hardware simulator,
• wherein the first processor simulator includes a first mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the first user program with the target digital circuitry,
• wherein the second processor simulator includes a second mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the second user program with the target digital circuitry,
• wherein determining the analyzed version of each user program includes decomposing the respective user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the respective target processor, the time calculating incorporating respective target processor's instruction timing,
• wherein determining the analyzed version of the first user program further includes identifying those parts of the first user program that include one or more references that might require a cache lookup,
• such that executing the analyzed version of each user program produces accurate timing information incorporating the respective target processor instruction timing including any cache effects in the case of the first target processor.

A method of simulating an electronic system that includes target digital circuitry and a target processor having a cache, the method comprising:

• (a) simulating execution of the user program on the target processor by executing the analyzed version of the user program on the host processor, the executing of the analyzed version including invoking a cache simulation process for a memory reference in the user program, and accumulating accurate timing information, the cache simulation process simulating the cache to account for the timing effects of a cache miss, and the accurate timing information including incorporating instruction timing;
• (b) simulating the target digital circuitry on a hardware simulator operating on the host computer system, the simulating of the target digital circuitry including accumulating accurate timing information;
• and
• (c) passing communication between the simulation of execution of the user program and the hardware simulator at significant events, including events that require interaction between the user program and the target digital circuitry.

A method for creating a processor model for simulating the operation of a target processor executing a user program, the processor model for use in a simulation design system operable on a host computer system to simulate an electronic system that contains target digital circuitry and the target processor, the target processor having a cache, the design system including a hardware simulator for simulating the digital circuitry on the host computer system, the method comprising:

• (a) creating a processor model shell for operation on the hardware simulator, the processor model shell accessing one or more signals of the target processor accessible to digital circuitry external to the target processor;
• (b) creating a software shell to provide the user program access to the processor signals coupled to the digital circuitry in the electronic system;
• and
• (c) creating target processor specific information for use in analyzing a user program to determine user program timing information such that when the user program is run on a processor simulator operating on the host computer system, the processor simulator accurately simulates execution, including providing timing, as if the user program was executing on the target processor, the timing taking into account instruction timing and pipeline effects,
• the user program analyzing including:
• decomposing the user program into linear blocks, calculating the time delay related to the delay that would be incurred by executing each linear block on the target processor with no cache misses, identifying those parts of the user program that have one or more references that might require a cache lookup, and inserting hooks into the user program to invoke the cache simulation process for any references that include a memory reference that requires a cache lookup, the time delay calculating using the target processor specific information.

A method of simulating on a host computer system the execution of a user program on a target processor having a cache, the method comprising:

• (a) decomposing the user program into linear blocks;
• (b) determining linear block timing information including the time delays that would be incurred executing each linear block of the user program on the target processor with no cache misses, the determining using characteristics of the target processor including instruction timing and cache characteristics, the block timing information taking into account instruction timing and pipeline effects;
• and
• (c) identifying those parts of the user program that include one or more references that might require a cache lookup;
• (d) inserting hooks into the user program to invoke a cache simulation process for any reference that includes a memory reference requiring a cache lookup;
• (e) combining the linear block timing information with the user program;
• (f) executing the combined user program and linear block timing information on the host computer system;
• and
• (g) simulating the target digital circuitry on a hardware simulator running on the host computer system,
• wherein execution of the combined user program and linear block timing information on the host computer system includes communicating with the hardware simulator when an event requires interaction of the user program with the target digital circuitry,
• such that the execution of the combined user program and linear block timing information on the host computer system simulates the execution of the user program on the target processor including providing accurate execution timing that takes into account instruction timing and cache effects.

A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor, and an accompanying user program to be executed on the target processor having a target processor bus, the design system comprising:

• a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;
• a hardware simulator to simulate the target digital circuitry using software executing on the host computer system;
• and
• an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,
• wherein the processor simulator includes
• a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry,
• wherein at least some of the operation of the target processor bus may be simulated by running a hardware model of the target processor bus on the hardware simulator,
• wherein determining the analyzed version of the user program includes:
• decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing,
• such that executing the analyzed version of the user program produces accurate timing information incorporating target processor instruction timing.

A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor, and an accompanying user program to be executed on the target processor, the target digital circuitry including target memory for the target processor, the design system comprising:

• a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;
• a hardware simulator to simulate the target digital circuitry using software executing on the host computer system;
• and
• an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,
• wherein the processor simulator includes
• a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry, and
• a memory mapper that translates between host memory addresses and target memory addresses, the translation using memory mapping information,
• wherein at least some of the operation of the target memory may be simulated by running a hardware model of the target memory on the hardware simulator,
• wherein the contents of the simulated target memory are stored on the host computer system,
• wherein determining the analyzed version of the user program includes:
• decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing,
• such that executing the analyzed version of the user program produces accurate timing information incorporating target processor instruction timing.

A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor, and an accompanying user program to be executed on the target processor, the design system comprising:

• a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;
• a hardware simulator to simulate the target digital circuitry using software executing on the host computer system;
• and
• an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,
• wherein the processor simulator includes
• a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry, and
• a memory allocation simulator that allocates memory on the host computer system while simulating the allocation of memory by the target processor,
• wherein determining the analyzed version of the user program includes:
• decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing, and
• inserting hooks in the user program to invoke the memory allocation simulator during execution of the analyzed program that correspond to dynamic memory allocations that would occur if the user program was being executed on the target processor, and
• such that executing the analyzed version of the user program produces accurate timing information incorporating target processor instruction timing.

A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor, and an accompanying user program to be executed on the target processor, the target digital circuitry including one or more devices coupled to the target processor, each device having a target address, the design system comprising:

• a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;
• a hardware simulator to simulate the target digital circuitry using software executing on the host computer system;
• and
• an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,
• wherein the processor simulator includes
• a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry, and
• wherein determining the analyzed version of the user program includes:
• decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing, and
• identifying those parts of the user program that include one or more references that might require a read or write to a device;
• such that executing the analyzed version of the user program
• (i) causes the processor simulator to communicate with the hardware simulator via the communication mechanism to cause the device to be written to or read from for any reference that is a device reference requiring a read or write to a device, and
• (ii) produces accurate timing information incorporating target processor instruction timing.