Shift redundancy scheme for wordlines in memory circuits

A wordline row redundancy scheme circuitry, comprising:

• a row shift circuit having row shift circuit input lines, row shift circuit control circuitry, and a row shift circuit output line corresponding with a row shift control line;
• the row shift circuit input lines being adapted to carry electrical signals indicative of a spare wordline address;
• a row decoder circuit electrically coupled to the row shift circuit by the row shift control line, the row shift circuit configured to apply a first row shift control signal level to the row shift control line, in the event that row shift redundancy is not desired and configured to apply a second row shift control signal level to the row shift control line, in the event that row shift redundancy is desired, said first and second row shift control signal levels have distinguishing characteristics;
• a first transistor, responsive to said first row shift control signal, having a first transistor control electrode electrically coupled to the row shift control line, the first transistor further being electrically coupled in series between an address selection transistor and a first wordline select line;
• and
• a second transistor, responsive to said second row shift control signal, having a second transistor control electrode electrically coupled to the row shift control line, the second transistor further being electrically coupled in series between said address selection transistor and a second wordline select line.

A method of performing a shift row redundancy scheme for a memory circuit, comprising the steps of:

• (a) detecting a defective memory cell included within a wordline of the memory circuit;
• (b) generating a row shift control signal for a wordline address selection control circuit associated with the wordline having the defective memory cell in response to detection of the defective memory cell;
• (c) actuating control circuitry associated with said wordline having the defective memory cell based upon generation of said row shift control signal;
• and
• (d) shifting the wordline select signal for said wordline to a wordline select line associated with an adjacent wordline by forming a conductive path between a wordline driver line associated with said wordline and said wordline select line associated with said adjacent wordline.