Operational amplifier with digital offset calibration
AssigneeHewlett-Packard Company
InventorsFrederick A. Perner, Kenneth J. Eldredge, Lung T. Tran
Life of this patent
Estimating the term…
Abstract
An operational amplifier includes transistors for providing a controlled current path. At least one of the transistors is in an isolated well in a substrate. Offset of the operational amplifier is corrected by applying a back gate bias voltage to at least one isolated well and changing impedance of the transistors. The proper back gate bias voltage and transistor impedance are determined by incrementally adjusting the back gate bias voltage and then incrementally adjusting the transistor impedance. Calibration values are stored in register memory. Such calibration may be performed by an auto offset calibration process.
Claims26
An integrated circuit having a calibration mode of operation and a normal mode of operation, the circuit comprising:
- an operational amplifier including a plurality of transistors for providing a controlled current path, at least some of the transistors being in isolated wells in a substrate;
- a programmable calibration circuit, responsive to a digital value, for performing at least one of (a) providing a back gate bias voltage to at least one isolated well and (b) adjusting impedance of the transistors providing the controlled current path, level of the back gate bias voltage and an amount of impedance adjustment being determined by the digital value, whereby different digital values may be supplied to the programmable calibration circuit during the calibration mode of operation;
- a test circuit including a test signal source for generating a test signal during the calibration mode of operation;
- and
- memory for storing a digital value that causes an output signal from the operational amplifier to be within a desired limit of the test signal during the calibration mode, the memory providing the stored value to the calibration circuit during the normal mode of operation.
An integrated circuit comprising:
- an operational amplifier including a plurality of transistors, at least some of the transistors being in isolated wells in a substrate;
- a first circuit, responsive to a first digital number, for applying a back gate bias voltage to at least one isolated well, level of the back gate bias voltage being determined by the first digital number;
- a second circuit responsive to a second digital number for adjusting impedance of the transistors, amount of the impedance adjustment being determined by a second digital number;
- and
- memory for supplying the first and second digital numbers to the first and second circuits, the digital numbers causing offset of the amplifier to be calibrated within a desired limit.
A method of calibrating offset error in an operational amplifier, the amplifier including at least one transistor in an isolated well, the method comprising the steps of:
- generating a test signal;
- supplying an input signal to the operational amplifier;
- comparing an output signal of the operational amplifier to the test signal;
- adjusting at least one of (a) back gate bias voltage to at least one isolated well and (b) transistor impedance;
- and
- storing a number that corresponds to a back gate bias and transistor impedance that causes the output signal to be within an acceptable limit of the test signal.
Dependencies are inferred from the claim text.