Open loop supply independent digital/logic delay circuit

A delay circuit for minimizing a variation in a delay period of a delayed signal comprising:

• a delay stage to receive an input signal and to generate the delayed signal which is delayed from the input signal by the delay period;
• a bias circuit coupled to said delay stage to control a delay stage current in said delay stage, in which a supply voltage to said delay stage and the delay stage current determine the delay;
• said bias circuit coupled to the supply voltage to provide a bias current having a fixed component and a variable component, wherein the fixed component of the bias current remains constant when the supply voltage varies, but the variable component of the bias current changes proportionately to the variation in the supply voltage;
• and
• the bias current coupled to control the delay stage current to adjust the delay stage current proportionately to variations in the supply voltage to minimize changes in the delay when the supply voltage varies.

An apparatus to provide analog-to-digital or digital-to-analog conversion comprising:

• a switching circuit to sample a digital signal for conversion to an analog signal or to sample an analog signal and for conversion to a digital signal;
• a delay circuit, having one or more delay stages, for providing two clocking signals to clock sampling switches of said switching circuit, but in which a second clocking signal follows a first clocking signal by a predetermined delay, said delay circuit minimizing a variation in the predetermined delay;
• a bias circuit coupled to the one or more delay stages to control a delay stage current in each of the delay stages, in which a supply voltage to each delay stage and the delay stage current for each stage determine the predetermined delay;
• said bias circuit coupled to the supply voltage to provide a bias current having a fixed component and a variable component, wherein the fixed component of the bias current remains constant when the supply voltage varies, but the variable component of the bias current changes proportionately to the variation in the supply voltage;
• and
• the bias current coupled to control each delay stage current to adjust each delay stage current proportionately to the variation in the supply voltage to minimize changes in the predetermined delay when the supply voltage varies.

A method to provide a delay in a circuit in which a timing of the delay is independent of supply voltage variation comprising:

• receiving an input signal;
• generating a delayed signal in response to the input signal in a delay stage, in which the delayed signal has a predetermined delay from the input signal;
• providing a bias current to control a delay stage current in the delay stage in which a supply voltage to the delay stage and the delay stage current determine the predetermined delay;
• the bias current sourced from the supply voltage and having a fixed component and a variable component, wherein the fixed component of the bias current remains constant when the supply voltage varies, but the variable component of the bias current changes in proportionately to the variation in the supply voltage;
• and
• the bias current coupled to control the delay stage current to adjust the delay stage current proportionately to the variation in the supply voltage to minimize changes in the predetermined delay when the supply voltage varies.