Loading patent…
AssigneeMicron Technology, Inc.
InventorsZhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
Estimating the term…
Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
A method of selectively removing material from a semiconductor substrate comprising:
A method of selectively removing material from a semiconductor substrate comprising:
A method of selectively removing material from a semiconductor substrate comprising:
A method of selectively removing material from a semiconductor substrate comprising:
A method of selectively removing material from a semiconductor substrate comprising:
A method of removing material from a semiconductor substrate, comprising:
A method of selectively removing material from a semiconductor substrate, comprising:
A method of removing material from a semiconductor substrate, comprising:
A method of selectively removing material from a semiconductor substrate comprising:
A method of selectively removing material from a semiconductor substrate, comprising:
A method of forming an interconnect structure on a semiconductor substrate, comprising:
A method of forming a capacitor storage node on a semiconductor substrate, comprising:
A method of forming an interconnect structure on a semiconductor substrate in a CMOS process flow, comprising:
A method of forming a shaped structure on a semiconductor substrate, the method comprising:
A method of forming a MOS surround-gate transistor on a semiconductor substrate, comprising:
A method of forming a stacked capacitor storage node on a semiconductor substrate, the method comprising:
A method of forming a shaped structure on a semiconductor substrate, comprising:
A method of forming an interconnect structure on a semiconductor substrate, comprising:
A method of forming a storage node of a stacked capacitor on a semiconductor substrate, comprising:
A method of forming a storage node of a stacked capacitor on a semiconductor substrate, comprising:
A method of forming a shaped structure on a semiconductor substrate, comprising:
A method of forming a structure in a semiconductor substrate, comprising:
A method of selectively forming a layer of a material on an exposed horizontal surface of a semiconductor substrate, comprising:
A method of forming an interconnect line on a semiconductor substrate, comprising:
A method of forming an interconnect line on a semiconductor substrate, comprising:
Dependencies are inferred from the claim text.