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US 6,260,137 B1Granted
Data processing unit with digital signal processing capabilities
AssigneeSiemens Aktiengesellschaft
InventorsRod G. Fleck, Daniel Martin
Life of this patent
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Abstract
The present invention relates to a data processing unit comprising a register file, a register load and store buffer connected to the register file, a single memory, and a bus having at least first and second word lines to form a double word wide bus coupling the register load and store buffer with said single memory. The register file at least two sets of registers whereby the first set of registers can be coupled with one of the word lines and the second set of registers can be coupled with the respective other word lines, a load and store control unit for transferring data from or to the memory.
Claims24
Data processing unit comprising:
- a register file with a plurality of word-wide registers, whereby a word having a predefined number of bits,
- a register load and store buffer connected to said register file,
- a memory,
- a bus having at least first and second word lines to form a double word wide bus coupling said register load and store buffer with said memory, whereby said register file has at least two sets of registers,
- coupling means, so that said first set of registers can be coupled with one of said word lines and said second set of registers can be coupled with the respective other word lines,
- a load and store control unit for transferring data from or to said memory, wherein said load and store control unit is configured to, in response to a single instruction for the data processing unit, load one word from said memory and to split it into two half-words which are stored in one half of a first register from said first set of registers and in a corresponding half of a second register from said second set of registers. respectively.
3 more elements
Data processing unit comprising:
- a register file with a plurality of word-wide registers, whereby a word having a predefined number of bits,
- a register load and store buffer connected to said register file,
- a memory,
- a bus having at least first and second word lines to form a double word wide bus coupling said register load and store buffer with said memory, whereby said register file has at least two sets of registers,
- coupling means, so that said first set of registers can be coupled with one of said word lines and said second set of registers can be coupled with the respective other word lines,
- a load and store control unit for transferring data from or to said memory, wherein said load and store control unit has means to load one word from said memory and to split it into two half-words which are stored in a first register from said first set of registers and in a second register from said second set of registers, wherein said load and store control unit further comprises means to load said half-words into a lower half of a register and to sign fill the upper half of said register.
3 more elements
Data processing unit comprising:
- a register file with a plurality of word-wide registers whereby a word having a predefined number of bits,
- a register load and store buffer connected to said register file,
- a memory,
- a bus having at least first and second word lines to form a double word wide bus coupling said register load and store buffer with said memory, whereby said register file has at least two sets of registers,
- coupling means, so that said first set of registers can be coupled with one of said word lines and said second set of registers can be coupled with the respective other word lines,
- a load and store control unit for transferring data from or to said memory, wherein said load and store control unit has means to load one word from said memory and to split it into a plurality of partial-words, each partial word is stored in one of said registers of each set of registers, respectively, wherein said load and store control unit further comprises means to load said partial-words into one part of a register and to fill the remaining part of said register with zeros.
3 more elements
Data processing unit comprising:
- a register file comprising a plurality of sets of word-wide registers, wherein a word has a predefined number of bits,
- a register load and store buffer coupled to said register file,
- a memory,
- a bus comprising a plurality of word lines to form an at least double word-wide bus coupling said register load and store buffer with said memory,
- a logic configured to couple a first set of registers with one of said plurality of word lines and to couple a second set of registers with another of said plurality of word lines,
- a load and store control unit configured to transfer data from or to said memory, wherein said load and store control unit is further configured to load one word from said memory, separate said one word into a plurality of partial words, and store said partial words into a plurality of said word-wide registers, each of said plurality of said word-wide registers storing no more than one of said partial words, and said partial words each stored at a same positional portion within its respective word-wide register, whereby gaps are created in said respective word-wide registers, the gaps being portions of said respective word-wide registers other than said same positional portion.
3 more elements
Data processing unit comprising:
- a register file comprising a plurality of sets of registers, each register being at least word wide, wherein a word has a predefined number of bits,
- a register load and store buffer coupled to said register file,
- a memory,
- a bus comprising a plurality of word lines to form an at least double word-wide bus coupling said register load and store buffer with said memory,
- a logic configured to couple a first set of registers with one of said plurality of word lines and to couple a second set of registers with another of said plurality of word lines,
- a load and store control unit configured to transfer data from or to said memory, wherein said load and store control unit is further configured execute an instruction that instructs the data processing unit to load one word from said memory, separate said one word into a plurality of partial words, and store said partial words into a plurality of said registers wherein said instruction also instructs the data processing unit to zero fill or sign fill.
3 more elements
Dependencies are inferred from the claim text.