Method and apparatus for TLB memory ordering

A method that uses a memory ordering protocol for specific pages of memory, comprising:

• generating a translation lookaside buffer (TLB) entry, said TLB entry comprises data address information and a memory ordering tag, said data address information further comprises a page frame number, said memory ordering tag further comprising information that identifies the address of the data to be accessed as located in a region of memory in which memory instructions either can be weakly ordered or must be strongly ordered;
• and
• interpreting said memory ordering tag of said TLB entry to associate said memory addresses on said page frame number with either a first or a second memory model, said first memory model further comprising logic to process all memory accesses to addresses located on said page frame number in accordance with a strong memory model, said second memory model further comprising logic to process all memory accesses to addresses located on said page frame number in accordance with a weak memory model.

A system that defines a memory ordering protocol for specific pages of memory, comprising:

• a translation lookaside buffer (TLB) entry, said TLB entry comprises data address information and a memory ordering tag, said data address information further comprising a page frame number, said memory ordering tag further comprising information that identifies the address of the data to be accessed as located in a region of memory in which memory instructions either can be weakly ordered or must be strongly ordered;
• and
• first and second memory models associated with said memory ordering tag, said first memory model further comprising logic to associate and process all memory addresses located on said page frame number in accordance with a strong memory model, said second memory model further comprising logic to associate and process all memory addresses located on said page frame number in accordance with a weak memory model.

A memory page tagging apparatus that invokes either a strong memory ordering protocol or a weak memory ordering protocol that processes memory instructions on specified pages of memory, comprising:

• a translation lookaside buffer (TLB) entry, said TLB entry comprises data address information and a memory ordering tag, said data address information further comprising a page frame number, said memory ordering tag further comprising information that identifies the address of the data to be accessed as located in a region of memory in which memory instructions either can be weakly ordered or must be strongly ordered;
• and
• first and second memory models associated with said memory ordering tag, said first memory model further comprising logic to associate and process all memory addresses located on said page frame number in accordance with a strong memory model, said second memory model further comprising logic to associate and process all memory addresses located on said page frame number in accordance with a weak memory model.