Single integrated circuit embodying a risc processor and a digital signal processor

A method of image identification comprising the steps of:

• disposing on a single integrated circuit a digital signal processor having a first set of data processing structures capable of data processing according to a first instruction set, a reduced instruction set computer processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set, an external interface connected to said first and second data processors and connectable to devices external to said single integrated circuit, wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets;
• connecting a memory to said external interface;
• and
• disposing in said memory a first set of instructions in said first instruction set and a second set of instructions in said second instruction set, said first set of instructions controlling operation of said digital signal processor and said second set of instructions in said second instruction set controlling operation of said reduced instruction set computer processor cooperatively to perform image recognition.

A method of image creation comprising the steps of:

• disposing on a single integrated circuit a digital signal processor having a first set of data processing structures capable of data processing according to a first instruction set, a reduced instruction set computer processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set, an external interface connected to said first and second data processors and connectable to devices external to said single integrated circuit, wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets;
• connecting a memory to said external interface;
• and
• disposing in said memory a first set of instructions in said first instruction set and a second set of instructions in said second instruction set, said first set of instructions controlling operation of said digital signal processor and said second set of instructions in said second instruction set controlling operation of said reduced instruction set computer processor cooperatively to perform image creation.

A method of data processing comprising the steps of:

• disposing on a single integrated circuit a digital signal processor having a first set of data processing structures capable of data processing according to a first instruction set, a reduced instruction set computer processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set, an external interface connected to said first and second data processors and connectable to devices external to said single integrated circuit, wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets;
• connecting a memory to said external interface;
• and
• disposing in said memory a first set of instructions in said first instruction set and a second set of instructions in said second instruction set, said first set of instructions controlling operation of said digital signal processor to perform two dimensional array processing and said second set of instructions in said second instruction set controlling operation of said reduced instruction set computer processor to perform information and/or display list processing.

A single integrated circuit comprising:

• a first data processor having a first set of data processing structures capable of data processing according to a first instruction set;
• a second data processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set;
• a first memory bank connected to said first data processor storing instructions in said first instruction set;
• a second memory bank connected to said second data processor storing instructions in said second instruction set;
• said first and second memory banks being configured as respective first and second instruction caches;
• said first data processor further including:
• a first program counter storing an address of a next instruction in said first instruction set to be executed by said first data processor,
• a first instruction cache logic circuit connected to said program counter and said first instruction cache for determining if the instruction corresponding to the address stored in said first program counter is stored in said first instruction cache;
• said second data processor further including:
• a second program counter storing an address of a next instruction in said second instruction set to be executed by said second data processor,
• a second instruction cache logic circuit connected to said second program counter and said second instruction cache for determining if the instruction corresponding to the address stored in said second program counter is stored in said second instruction cache;
• an external interface connectable to devices external to said single integrated circuit;
• and
• a transfer controller connected to said first and second data processors, said external interface and said first and second memory banks, said transfer controller transferring an instruction via said external interface corresponding to the address stored in said first program counter from a device external to said single integrated circuit to said first instruction cache if said first instruction cache logic circuit determines said instruction is not stored in said first instruction cache, and said transfer controller transferring an instruction via said external interface corresponding to the address stored in said second program counter from a device external to said single integrated circuit to said second instruction cache if said second instruction cache logic circuit determines the instruction is not stored in said second instruction cache;
• wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets, said first data processor operating in accordance with instructions in said first instruction set recalled from said first memory bank and said second data processor operating in accordance with instructions in said second instruction set recalled from said second memory bank.

A single integrated circuit comprising:

• a first data processor having a first set of data processing structures capable of data processing according to a first instruction set;
• a second data processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set;
• a first memory bank connected to said first data processor storing instructions in said first instruction set;
• a second memory bank connected to said second data processor storing instructions in said second instruction set;
• a plurality of third memory banks, each third memory bank connected to said first and second data processors permitting a selected one of said first and second data processor to read data from or write data to said third memory bank;
• at least a fourth memory bank and a fifth memory of said plurality of third memory banks being configured as respective first and second data caches;
• said first data processor further including:
• a first address register storing an address of a next data to be read or written by said first data processor,
• a first data cache logic circuit connected to said first address register and said first data cache for determining if the data corresponding to the address stored in said first address register is stored in said first data cache;
• said second data processor further including:
• a second address register storing an address of a next data to be read or written by said second data processor,
• a second data cache logic circuit connected to said second address register and said second data cache for determining if the data corresponding to the address stored in said second address register is stored in said second data cache;
• an external interface connectable to devices external to said single integrated circuit;
• and
• a transfer controller connected to said first and second data caches and to said external interface, said transfer controller transferring data via said external interface corresponding to the address stored in said first address register from a device external to said single integrated circuit to said first data cache if said first data cache logic circuit determines said data is not stored in said first data cache upon a data read, said transfer controller transferring data via said external interface corresponding to the address stored in said first address register from said first data cache to a device external to said single integrated circuit if said first data cache logic circuit determines said data is not stored in said first data cache upon a data write, said transfer controller transferring data via said external interface corresponding to the address stored in said second address register from a device external to said single integrated circuit to said second data cache if said second data cache logic circuit determines said data is not stored in said second data cache upon a data read, and said transfer controller transferring data via said external interface corresponding to the address stored in said second address register from said second data cache to a device external to said single integrated circuit if said second data cache logic circuit determines said data is not stored in said second data cache upon a data write;
• where said first and second data processors are capable of independent operations on disjoint instructions and data sets, said first data processor operates in accordance with instructions in said first instruction set recalled from said first memory bank and said second data processor operates in accordance with instructions in said second instruction set recalled from said second memory bank.