Equipotential sense methods for resistive cross point memory cell arrays
AssigneeHewlett-Packard Company
InventorsLung T Tran, Frederick A Perner, James A Brug
Life of this patent
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Abstract
An equal potential may be applied to a selected bit line and unselected bit lines during a read operation on a memory cell in a resistive cross point array. In the alternative, an equal potential may be applied to the selected bit line and unselected word lines.
Claims30
A method of performing a read operation on a selected memory cell in a resistive cross point array of memory cells, a plurality of word lines crossing rows of the memory cells, a plurality of bit lines crossing columns of the memory cells, the method comprising the steps of:
- applying a first potential to a selected bit line crossing the selected memory cell and a second potential to a selected word line crossing the selected memory cell;
- applying a third potential to a subset of unselected word and bit lines, the third potential being equal to the first potential;
- and
- determining the resistance state of the selected memory cell while the potentials are being applied to the selected lines and subset of unselected lines.
Apparatus for reading a selected memory cell in a resistive cross point array of memory cells, a plurality of word lines crossing rows of the memory cells, a plurality of bit lines crossing columns of the memory cells, the apparatus comprising:
- means for applying a first potential to a selected bit line crossing the selected memory cell and a second potential to a selected word line crossing the selected memory cell;
- means for applying a third potential to a subset of unselected word and bit lines, the third potential being equal to the first potential;
- and
- means for determining the resistance state of the selected memory cell while the potentials are being applied to the selected lines and the subset of unselected lines.
A data storage device comprising:
- a resistive cross point array of memory cells;
- a plurality of word lines extending along rows of the array;
- a plurality of bit lines extending along columns of the array;
- and
- a circuit for sensing resistance states of selected memory cells during read operations on the selected memory cells, the circuit applying a first potential to selected bit lines, a second potential to selected word lines and a third potential to subsets of unselected word and bit lines, the third potential being equal to the first potential.
Apparatus for reading a selected memory cell in a resistive cross point array of memory cells, the selected memory cell being at a cross point of first and second selected traces, the apparatus comprising:
- means for applying a first potential to the first trace and a second potential to the second trace;
- means for applying a third potential to a subset of traces not crossing the selected memory cell, the third potential being equal to the first potential;
- and
- means for determining the resistance state of the selected memory cell while the potentials are being applied to the selected traces and the subset of unselected traces.
A data storage device comprising:
- a resistive cross point array of memory cells;
- a plurality of first traces lines extending along the array in a first direction;
- a plurality of second traces extending along the array in a second direction, each memory cell being at a cross point of one of the first traces and one of the second traces;
- and
- a circuit for sensing resistance states of selected memory cells during read operations on the selected memory cells, the circuit applying a first potential to the first traces crossing the selected memory cells, a second potential to the second traces crossing the selected memory cells, and a third potential to subsets of traces not crossing the selected memory cells, the third potential being equal to the first potential.
Dependencies are inferred from the claim text.