Read and write operations using constant row line voltage and variable column line load

A read operation for a memory, comprising:

• biasing a selected row line at a first voltage, wherein the selected row line is coupled to a control gate of a selected memory cell, and the first voltage is higher than any threshold voltage used to represent data in the memory;
• connecting a sense amplifier to a selected column line that is coupled to the selected memory cell;
• applying a selected load to the selected column line;
• determining a state of the sense amplifier while the selected row line is at the first voltage and the selected load is applied to the selected column;
• in response to the sense amplifier having a first state, changing the selected load and repeating the applying and determining steps, wherein changing the selected load comprises operating a counter that provides a count signal as a control signal for a variable load;
• and
• in response to the sense amplifier having a second state, generating a read value according to the selected bias.

A memory comprising:

• a memory array including rows and columns of memory cells, wherein each row of the array has a row line coupled to memory cells in the row, and each column has a column line coupled to memory cells in the column;
• a column decoder coupled to the column lines of the memory array;
• a first variable load between the column decoder and a source of a first voltage;
• and
• a counter coupled to the first variable load, wherein a count signal from the counter controls the first variable load.

A write operation for a non-volatile multi-level memory, comprising:

• (a) applying a programming pulse to a selected memory cell to change a threshold voltage of the selected memory cell;
• (b) sensing a state of a sense amplifier connected to the selected memory cell when the selected memory cell is biased for sensing;
• (c) repeating the applying and sensing steps until the sensing first determines the sense amplifier has a first state;
• (d) sensing the state of the sense amplifier again to confirm the first determination whether the sense amplifier had the first state;
• (e) in response to failing to confirm, applying a further programming pulse to the selected memory cell to change the threshold voltage of the selected memory cell;
• and
• (f) in response to confirming the first determination, ending the write operation.

A write operation for a multi-bit-per-cell non-volatile memory, comprising:

• biasing a selected row line at a first voltage, wherein the selected row line is coupled to a control gate of a selected memory cell;
• performing a programming operation by connecting a first load to a selected column line, wherein the selected column line is coupled to the selected memory cell and the first load provides a programming current that changes a threshold voltage of the selected memory cell during the programming operation;
• selecting a second load that corresponds to a multi-bit value that the write operation writes in the selected memory cell;
• performing a verify operation that comprises:
• connecting the second load and a sense amplifier to the selected column line, wherein the selected row line remains at the first voltage during the verify operation;
• and determining a state of the sense amplifier while the selected row line is at the first voltage and the second load is connected to the selected column;
• in response to the sense amplifier having a first state during the verify operation, repeating the programming operation and the verify operation;
• and
• ending the write operation in response to the sense amplifier having a second state during the verify operation.

A multi-bit-per-cell memory comprising:

• a memory array including rows and columns of memory cells, wherein each row of the array has a row line coupled to memory cells in the row, and each column has a column line coupled to memory cells in the column;
• a column decoder coupled to the column lines of the memory array;
• a first variable load coupled to the column decoder;
• a sense amplifier coupled to the column decoder;
• and
• a control circuit connected to the first variable load, wherein for a write operation, the control circuit receives a multibit value to be written in a selected memory cell and controls the first variable load to bias a selected column line for a verify cycle of the write operation, the control circuit controlling the first variable load so that a trip point of the sense amplifier during the verify cycle depends on the multibit value.