Static random access memory (SRAM) circuit
AssigneeNEC Corporation
InventorHiroyuki Takahashi
Life of this patent
Estimating the term…
Abstract
A static random access memory (SRAM) circuit includes four-transistor memory cells and is capable of high-speed reliable read operations. According to one embodiment, a SRAM circuit includes “n” memory cells (200-1 to 200-n) connected to digit line pairs (202-0 and 202-1). When selected, a memory cell (200-1 to 200-n) can draw an on current (Ion). When deselected, a memory cell (200-1 to 200-n) can draw a leakage current (Ioff) that can maintain a data value stored in a memory cell. High-speed and reliable operations may be achieved by meeting the following relationship: Ion>K*(n−1)*Ioff, where K is 1 or more.
Claims20
A static random access memory (SRAM) circuit, comprising:
- a number of n memory cells coupled to a digit line pair, where n is greater than 1, each memory cell including two driver transistors and two access transistors and drawing a current Ion when selected, and drawing a current Ioff when de-selected;
- wherein
- the number n and Ion and Ioff values of the memory cells satisfies the relationship Ion>K*(n−1)*Ioff, where K is at least one.
A static random access memory (SRAM) device, comprising:
- a plurality of memory cells each coupled to a digit line pair by a corresponding pair of access transistor, each memory cell having a de-selected state that maintains a stored data value by a leakage current flowing through one of the access transistors and a selected state that draws an on current through one of the access transistors, the on current of a selected memory cell coupled to the digit line pair being greater than the leakage current of the remaining de-selected memory cells coupled to the digit line pair.
A static random access memory (SRAM) circuit, comprising:
- a digit line pair;
- and
- n memory cells coupled to the digit line pair, each memory cell consisting of two access transistors and two driver transistors, each memory cell having a selected state in which the access transistors are turned on and an on current is drawn through one of the access transistors, each memory cell having a de-selected state in which the access transistors are turned off and a leakage current is drawn through one of the access transistors, the sum of all but one of the memory cell leakage currents being less than the on current of one memory cell.
Dependencies are inferred from the claim text.