Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction

A processor comprising:

• a branch scanner configured to identify a first branch instruction within a plurality of instructions;
• a branch history table coupled to said branch scanner, wherein said branch history table is configured to select a first branch prediction from a plurality of branch predictions stored therein responsive to said first branch instruction identified by said branch scanner;
• and
• a forward collapse unit coupled to said branch scanner and said branch history table, wherein said forward collapse unit is configured to indicate:
• (i) which instructions within said plurality of instructions and subsequent to said first branch instruction to cancel from a pipeline of said processor prior to executing said instructions, and (ii) which instructions within said plurality of instructions and subsequent to said first branch instruction to retain in said pipeline, said forward collapse unit responsive to said first branch prediction indicating taken and said first branch instruction having a forward branch target address within a predetermined range of a first branch fetch address corresponding to said first branch instruction.

A computer system comprising:

• a processor configured to fetch a plurality of instructions, wherein said processor is configured to identify a first branch instruction within said plurality of instructions, and wherein said processor is configured to:
• (i) cancel instructions from a pipeline of said processor prior to executing said instructions, and (ii) retain instructions within said plurality of instructions and subsequent to said first branch instruction in said pipeline, said processor configured to cancel and retain instructions responsive to predicting said first branch instruction taken and said first branch instruction having a forward branch target address within a predetermined range of a first branch fetch address corresponding to said first branch instruction;
• and
• an input/output (I/O) device coupled to said processor, wherein said I/O device is configured to communicate between said computer system and another computer system to which said I/O device is coupled.

A processor comprising:

• a branch prediction circuit configured to identify a first branch instruction within a plurality of instructions and to predict said first branch instruction;
• and
• a first circuit coupled to said branch prediction circuit, wherein said first circuit is configured, responsive to said first branch instruction having a forward target address within a predetermined range of a first branch fetch address corresponding to said first branch instruction and said branch prediction circuit predicting said first branch instruction taken:
• (i) to cancel a first one or more instructions within said plurality of instructions from a pipeline of said processor prior to executing said first one or more instructions, said first one or more instructions having fetch addresses between said first branch fetch address and said forward target address, and (ii) to retain a second one or more instructions in said pipeline, said second one or more instructions within said plurality of instructions and having fetch addresses which are not between said first branch fetch address and said forward target address.