US 6,256,715 B1Granted

System and method of performing gateway access

AssigneeMicro Unity Systems Engineering, Inc.

InventorCraig C. Hansen

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Abstract

A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. Memory area priority protection is achieved by employing a gateway instruction which includes a gateway register pointer and the priority level of the instruction. The gateway register holds a pointer to a specific entry point within a high priority area within memory at which the lower priority gateway instruction may enter it.

Claims14

Dependent claims

A computer system comprising:

a memory for storing processor instructions and data, said memory being partitioned into a plurality of areas having corresponding access privilege levels, said privilege levels defined for a plurality of types of memory access;
a processor for executing said processor instructions, said processor having associated privilege level states, indicating a current memory access privilege level;
a plurality of gateway processor instructions including an operation code which indicates an operation to be executed by said processor;
a plurality of gateway storage areas in said memory each for storing an entry point address which points to a series of instructions, a new privilege level, and a data address which points to data;
wherein executing one of said gateway instructions causes said processor to:
1) generate a first address to one of said gateway storage areas;
2) perform an access to said memory using said first address, said processor indicating one of said types of memory access and said current memory access privilege level;
3) begin executing said series of instructions at said entry point address, setting said current memory access privilege level to said new privilege level;
and
4) to load said data address into a processor register.

7 more elements

An access method in a computer system including a memory, a processor, and a program counter, said memory for storing processor instructions and data and being partitioned into a plurality of areas having corresponding access privilege levels, said privilege levels defined for a plurality of types of memory access, said processor for executing said processor instructions, and having associated privilege level states indicating a current memory access privilege level, and said program counter for storing an address of an instruction currently being executed by said processor, said method for accessing said memory area comprising the steps of:

storing an entry point address, a new privilege level, and a data address, said entry point address pointing to a series of instructions, and said data address pointing to data in a plurality of gateway storage areas in said memory;
and
executing a given processor instruction including an operation code which indicates an operation to be executed by said processor causing said processor to:
generate a first address to one of said gateway storage areas,
perform an access to said memory using said first address, said processor indicating one of said types of memory access and said current memory access privilege level,
begin executing said series of instructions at said entry point address, and set said current memory access privilege level to said new privilege level, and
load said data address into a processor register.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/570,397Filed 12 May 2000 · continuation
Priority: 10 Oct 1995
Granted: 3 Jul 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 12/0284
User address space allocation, e.g. contiguous or non contiguous base addressing: multiple user address space allocation, e.g. using different…
G06F 12/1045
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: associated with a data cache
G06F 12/1491
By checking the subject access rights: in a hierarchical protection system, e.g. privilege levels, memory rings
G06F
Computing and data processing