Semiconductor P-I-N detector
OwnerRengarajan Sudharsanan, Nasser H. Karaminventors
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Abstract
A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.
Claims14
A multilayer semiconductor P-I-N device for detecting gamma rays, the device comprising:
- an intrinsic wafer having a top surface and a bottom surface, the intrinsic wafer generating an electrical current as a function of impacting gamma rays,
- a non-doped semiconductor boundary layer overlying the top surface of the intrinsic wafer,
- a doped semiconductor layer overlying the non-doped semiconductor boundary layer, and
- an oppositely doped semiconductor layer overlying the bottom surface of the intrinsic wafer,
- wherein the non-doped semiconductor boundary layer positioned between the intrinsic wafer and the doped semiconductor layer reduces the diffusion of dopant into the intrinsic wafer, thereby reducing the leakage current through the P-I-N device.
A multilayer semiconductor P-I-N device for detecting high energy rays, the device comprising:
- an intrinsic wafer having a bottom surface and a top surface, the intrinsic wafer generating an electrical current as a function of impacting high energy rays,
- a deposited non-doped semiconductor boundary layer overlying the top surface of the intrinsic wafer,
- a doped semiconductor layer overlying the non-doped semiconductor boundary layer, and
- an oppositely doped semiconductor layer deposited on and overlying the bottom surface of the intrinsic wafer,
- wherein the non-doped semiconductor boundary layer positioned between the intrinsic wafer and the doped semiconductor layer reduces the diffusion of dopant into the intrinsic wafer, thereby reducing the leakage current through the P-I-N device.
Dependencies are inferred from the claim text.