Data phase locked loop circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHisao Katoh
Life of this patent
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Abstract
A phase comparator circuit reducing the effects of offset and jitter, and a data Phase Locked Loop circuit incorporating the phase comparator circuit. The phase comparator circuit includes a Delay Locked Loop circuit for outputting a delay, signal PLDTD with a delay according to an oscillation frequency of a voltage controlled oscillator, with respect to an input data PLDT, a D-type flip-flop for outputting a delay signal PLDTL by latching an input data PLCK according to an oscillation clock PLCK output from a voltage controlled oscillator, and a phase comparator for comparing phases of delay signals PLDTD and PLDTL.
Claims8
A phased locked loop (PLL) circuit comprising:
- a voltage controlled oscillator generating an oscillation clock having a frequency and including a plurality of first variable delay stages;
- a delay unit for outputting a first delay signal having a frequency and a phase, with a delay according to the frequency of said voltage controlled oscillator, of input data and including a plurality of second variable delay stages, said first and second variable delay stages being identical and respectively connected in cascade, wherein a delay control current supplied to switch sections of said first variable delay stages of said voltage controlled oscillator is also input to switch sections of said second variable delay stages;
- a latching unit for outputting a second delay signal having a frequency and a phase, by latching the input data according to the oscillation clock output by said voltage controlled oscillator;
- and
- a phase comparing unit for comparing the phase of the first delay signal to the phase of the second delay signal.
Dependencies are inferred from the claim text.