Method to form, and structure of, a dual damascene interconnect device

A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprising the steps of:

• a) depositing and exposing a first level via photo sensitive dielectric layer, having a thickness from about 7000 to 14,000 Å, over a semiconductor structure;
• b) depositing and exposing a first level trench photo sensitive dielectric layer, having a thickness from about 4000 to 7000 Å, over said first via photo sensitive dielectric layer;
• c) patterning and etching said exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers to form a first level dual damascene opening;
• said first level dual damascene opening comprising an integral first level via and metal line openings;
• d) forming a barrier layer within said first level dual damascene opening;
• e) depositing a first level conductor layer over said first level trench photo sensitive dielectric layer, filling said first level dual damascene opening;
• f) planarizing said first level conductor layer to form at least one first level dual damascene interconnect, said first level dual damascene interconnect having a first level horizontal conductor line and a first level vertical via stack;
• g) repeating steps a) to f) over said first level metal dual damascene interconnect n-1 times to form a dual damascene interconnect structure where n is the number of interconnect levels desired, and where a plurality of dual damascene structures may be formed having from n to n-1 levels of metal dual damascene interconnects;
• h) depositing and patterning a passivation layer over said nth conductor dual damascene interconnect layer to form openings in said passivation layer;
• and i) selectively stripping and removing a predetermined number of said via photo sensitive dielectric and trench photo sensitive dielectric layers beneath said passivation layer openings and between said plurality of dual damascene structures wherein the portion of said via photo sensitive dielectric underneath said horizontal metal lines of said stripped trench photo sensitive dielectric layers remains.

A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprising the steps of:

• a) spinning on, exposing, developing and ashing a first level photo sensitive dielectric layer over a semiconductor structure to form a first level dual damascene opening;
• said first level dual damascene opening comprising an integral first level via and metal line openings;
• b) depositing a first level conductor layer over said first level photo sensitive dielectric layer, filling said first level dual damascene opening;
• c) planarizing said first level conductor layer to form at least one first level dual damascene interconnect, said first level dual damascene interconnect having a first level horizontal conductor line and a first level vertical via stack;
• d) repeating steps a) to c) over said first level dual damascene interconnect n-1 times to form a dual damascene interconnect structure where n is the number of interconnect levels desired, and where a plurality of dual damascene structures may be formed having from n to n-1 levels of metal dual damascene interconnects;
• e) depositing and patterning a passivation layer over said nth metal dual damascene interconnect layer to form openings in said passivation layer;
• and
• f) selectively stripping and removing a predetermined number of said via photo sensitive dielectric and trench photo sensitive dielectric layers beneath said passivation layer openings and between said plurality of dual damascene structures wherein the portion of said via photo sensitive dielectric underneath said horizontal conductor lines of said stripped trench photo sensitive dielectric layers. remains.

An interconnect structure in a semiconductor device comprising;

• a semiconductor layer;
• at least one interconnect structure comprising a plurality of interconnects above said semiconductor layer;
• each said interconnect having a horizontal conductor line and a vertical via stack;
• air gaps adjacent said at least one interconnect structure, said air gaps formed within the interlevel and intralevel layers;
• and
• polymer supports under said conductor lines and adjacent said via stacks of said interconnects;
• whereby said polymer supports support and strengthen said at least one interconnect structure.

An interconnect structure in a semiconductor device comprising;

• a semiconductor layer;
• at least one interconnect structure comprising a plurality of dual damascene copper interconnects above said semiconductor layer;
• each said dual damascene copper interconnect having a horizontal conductor line and a vertical via stack;
• air gaps adjacent said at least one interconnect structure, said air gaps formed within the interlevel and intralevel layers;
• and
• polymer supports under said conductor lines and adjacent said via stacks of said dual damascene copper interconnects;
• whereby said polymer supports support and strengthen said at least one interconnect structure.