Method of manufacturing a nonvolatile memory

A method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a field-effect transistor having a gate insulated from the semiconductor body by a gate dielectric, and with a non-volatile memory element having a floating gate and a control gate, the floating gate being insulated from the semiconductor body by a floating gate dielectric and from the control gate by an inter-gate dielectric, the method comprising defining a first and a second active region of a first conductivity type adjoining the surface in the semiconductor body for the transistor and the memory element, respectively, and coating the surface with a first insulating layer providing the floating gate dielectric of the memory element;

• applying a silicon containing layer on the first insulating layer to form the floating gate of the memory element;
• then providing source and drain zones of a second conductivity type of the memory element in the semiconductor body and applying a second insulating layer at the second active region so as to provide the inter-gate dielectric of the memory element;
• applying a conductive layer on the second insulating layer to form the control gate of the memory element;
• and, with the formation of the floating gate and the floating gate dielectric of the memory element, providing the first active region with a sacrificial gate and a sacrificial gate dielectric of the transistor, respectively;
• then providing source and drain zones of the second conductivity type of the transistor together with the source and drain zones of the memory element and applying a dielectric layer and then removing said dielectric layer over at least part of its thickness by means of a material removing treatment until the silicon-containing layer at the first and the second active region is exposed;
• then removing the silicon-containing layer and the first insulating layer at the first active region, thereby forming a recess in the dielectric layer;
• applying a third insulating layer in said recess for providing the gate dielectric of the transistor at the first active region;
• then applying the conductive layer, thereby filling the recess at the first active region;
• and shaping the conductive layer into the gate of the transistor at the first active region and into the control gate of the memory element at the second active region.