US 6,249,893 B1Granted

Method and structure for testing embedded cores based system-on-a-chip

AssigneeAdvantest Corporation

InventorsRochit Rajsuman, Hiroaki Yamoto

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Abstract

A method of testing embedded cores in an integrated circuit chip having a microprocessor core, a memory core and other functional cores therein. The method includes the steps of; forming a plurality of registers in the integrated circuit chip, testing the microprocessor core by executing its instructions multiple times with pseudo random data and evaluating the results by comparing simulation results, applying a test program to the microprocessor core to generate a memory test pattern by the microprocessor core, applying the memory test pattern to the memory core by the microprocessor core and evaluating the response of the memory core by the microprocessor core, and testing the other functional cores by applying a function specific test pattern thereto by the microprocessor core and evaluating the resultant output signals of the functional cores.

Claims17

Dependent claims

A method for testing embedded cores in an integrated circuit chip having a microprocessor core, a memory core and other functional cores therein comprising the following steps of:

providing a plurality of registers to be used for testing the microprocessor core in the integrated circuit chip;
testing the microprocessor core by executing its instructions multiple times with pseudo random data and evaluating the results by comparing with simulation results;
applying a test program to the microprocessor core to generate a memory test pattern by the microprocessor core;
applying the memory test pattern to the memory core by the microprocessor core and evaluating the response of the memory core by the microprocessor core;
and
testing the other functional cores by applying a function specific test program thereto by the microprocessor core and evaluating the resultant output signals of the functional cores;
wherein the plurality of registers is comprised of a test control register for providing test instructions to an instruction decoder of the microprocessor core, a linear feedback shift register for providing test operand to an instruction execution unit of the microprocessor core, and a multi-input feedback shift register for receiving results from the instruction execution unit of the microprocessor core.

4 more elements

A structure for testing embedded cores in an integrated circuit chip having a microprocessor core, a memory core and other functional cores therein, comprising:

a test control register for providing test instructions to an instruction decoder of the microprocessor;
a first multiplexer for selecting either the test instructions from the test control register or instructions from an instruction fetch unit of the microprocessor;
a linear feedback shift register for providing test operand to an instruction execution unit of the microprocessor;
a second multiplexer for selecting either the test operand from the linear feedback shift register or operand from a main memory of the microprocessor;
a multi-input feedback shift register for receiving results from the instruction execution unit of the microprocessor;
and
a controller for providing the test instruction to the test control register and the linear feedback shift register, and evaluating an output signature of the multi-input feedback shift register by comparing the output signature with precomputed expected data;
and
means for providing a test program to the microprocessor core through an interface circuit for generating test patterns for the memory core or other functional cores;
wherein the memory core is provided with a memory test pattern generated by the microprocessor core and a resultant output of the memory core is evaluated by the microprocessor core, and the other functional cores are provided with a function specific test pattern by the microprocessor core and resultant output signals are evaluated by the microprocessor core.

7 more elements

Dependencies are inferred from the claim text.