Circuit and method for equalizing erase rate of non-volatile memory cells
AssigneeAMIC Technology Corporation
InventorsKou-Su Chen, Shih-Chun Fu, Jui-Te Chan
Life of this patent
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Abstract
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
Claims16
A method of equalizing erase rates of flash cells in a memory array, the flash cells each having a floating gate with an floating gate charge value, and which floating gate charge value is intended to be set to a target initial charge value prior to an erase operation, the method comprising:
- (a) generating a flash cell conditioning signal having a predetermined magnitude and duration;
- (b) adjusting the floating gate charge value of each of such flash cells using said conditioning signal, the floating gate charge value for any such flash cell being adjusted by said conditioning signal by a charge amount proportional to the floating gate charge value;
- wherein erase rates of flash cells with floating gate charge values substantially in excess of said target initial charge value are substantially affected by said flash cell conditioning signal, while erase rates of flash cells with floating gate charge values substantially below said target initial charge values are substantially unaffected by said flash cell conditioning signal;
- and
- further wherein steps (a) and (b) are repeated until the flash cell floating gate charge values substantially converge to the target initial charge value so that all of the flash cells can then be erased at an approximately uniform erase rate by a subsequent erase operation.
A circuit for equalizing erase rates of flash cells in a memory array, the flash cells each having a floating gate with an floating gate charge value, and which floating gate charge value is intended to be set to a target initial charge value prior to an erase operation, the circuit comprising:
- (a) a flash cell controller circuit configured to generate a set of control signals for controlling a magnitude, duration and sequence associated with a flash cell conditioning signal;
- (b) a flash cell conditioning signal generator for generating said flash cell conditioning signal in response to said set of control signals;
- and
- wherein said flash cell conditioning signal is used for adjusting the floating gate charge value of each of such flash cells and operates to adjust the floating gate charge value for any such flash cell by a charge amount proportional to an original starting floating gate charge value;
- and
- further wherein erase rates of flash cells with floating gate charge values substantially in excess of said target initial charge value are substantially affected by said flash cell conditioning signal, while erase rates of flash cells with floating gate charge values substantially below said target initial charge values are substantially unaffected by said flash cell conditioning signal.
Dependencies are inferred from the claim text.