High slew rate input differential pair with common mode input to ground

A circuit, comprising:

• a first transistor and a second transistor of a first type, each of said first and second transistors having a control terminal, each control terminal being coupled to a first input voltage terminal;
• a third transistor and a fourth transistor of said first type, each of said third and forth transistors having a control terminal, each control terminal being coupled to a second input voltage terminal;
• each of said first, second, third, and fourth transistors having a first current handling terminal, each first current handling terminal being coupled to a first reference voltage;
• a first current mirror having a first bias terminal coupled to a second current handling terminal of said first transistor and a second bias terminal coupled to a second current handling terminal of said second transistor, said first current mirror having a first output terminal;
• a second current mirror having a first bias terminal coupled to a second current handling terminal of said fourth transistor and a second bias terminal coupled to a second current handling terminal of said third transistor, said second current mirror having a second output terminal;
• a first resistor coupled between said second current handling terminals of said second and third transistors;
• a fifth transistor and a sixth transistor of a second type opposite said first type, each of said fifth and sixth transistors having a control terminal, each control terminal being coupled to said first input voltage terminal;
• a seventh transistor and an eighth transistor of said second type, each of said seventh and eighth transistors having a control terminal, each control terminal being coupled to said second input voltage terminal;
• each of said fifth, sixth, seventh, and eighth transistors having a first current handling terminal, each first current handling terminal being coupled to a second reference voltage;
• a third current mirror having a first bias terminal coupled to a second current handling terminal of said fifth transistor and a second bias terminal coupled to a second current handling terminal of said sixth transistor, said third current mirror having a third output terminal;
• a fourth current mirror having a first bias terminal coupled to a second current handling terminal of said eighth transistor and a second bias terminal coupled to a second current handling terminal of said seventh transistor, said fourth current mirror having a fourth output terminal;
• and
• a second resistor coupled between said second current handling terminals of said sixth and seventh transistors;
• wherein said transistors of said first type are PMOs transistors, and said transistors of said second type are NMOS transistors, and when a differential voltage is applied to said first input voltage terminal and said second input voltage terminal, a first voltage develops across said first resistor and a second voltage develops across said second resistor, each of said first and second voltages having a value substantially equal to said differential voltage.