Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system

A semiconductor integrated circuit device having a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adiustina circuit for supplying said control command, set active for a predetermined period, as a DRAM control signal to said DRAM core, wherein

• said timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates said DRAM control signal by setting said control command active in a prescribed operation cycle only for a period starting at a first predetermined clock pulse of a first clock of said n clocks and ending at a second predetermined clock pulse of a second clock of said n clocks, wherein said timing adjusting circuit includes:
• a common counter for counting one of said n clocks, or said reference clock, as a common clock;
• a first logic gate for enabling one of said n clocks for output only for a period during which the count value of said common counter shows a first value;
• a second logic gate for enabling one of said n clocks for output only for a period during which the count value of said common counter shows a second value;
• and
• a timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time that the output of said first logic gate becomes active and lasting until the time that the output of said second logic gate becomes active.

A timing adjusting circuit for generating n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and for generating a control signal by being set in an active state in a prescribed operation cycle only for a period starting at a first predetermined clock pulse of a first clock of said n clocks and ending at a second predetermined clock pulse of a second clock of said n clocks wherein said timing adiusting circuit includes:

• a first counter for counting said first clock;
• a second counter for counting said second clock;
• and
• a timing buffer circuit for generating said control signal by being set in an active state for a period starting from the time that the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value.

A timing adiustinq circuit for generating n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and for generating a control signal by being set in an active state in a prescribed operation cycle only for a period starting at a first predetermined clock pulse of a first clock of said n clocks and ending at a second predetermined clock pulse of a second clock of said n clocks, wherein said timing adjusting circuit includes:

• a common counter for counting one of said n clocks, or said reference clock, as a common clock;
• a first logic gate for enabling one of said n clocks for output only for a period during which the count value of said common counter shows a first value;
• a second logic gate for enabling one of said n clocks for output only for a period during which the count value of said common counter shows a second value;
• and
• a timing buffer circuit for generating said control signal by being set in an active state for a period starting from the time that the output of said first logic gate becomes active and lasting until the time that the output of said second logic gate becomes active.