Chipset configured to perform data-directed prefetching

Abstract

A chipset is configured to communicate between one or more processors and other components of the computer system, including a main memory. The chipset communicates read memory operations initiated by the processors to the main memory, and returns the data provided therefrom to the processors. Additionally, the chipset includes circuitry configured to select a portion of the data and to generate a prefetch address using the data. Accordingly, a pointer included in the data can be used to generate a prefetch address. The prefetching does not rely on observing the data access pattern. Instead, the data being transferred in response to a memory operation is used to generate a prefetch address (i.e. “data-directed prefetching”). In one embodiment, various programmable features are included in the chipset to specify which portion of the data to select, when to perform prefetching, etc. Accordingly, the prefetching mechanism is flexible to adapt to a variety of data structures and patterns of access to those data structures. By implementing the data-directed prefetching algorithm in the chipset, the data can be selected and a prefetch address generated early in the performance of the memory operation. Accordingly, the effective memory latency of the prefetched data may be substantially reduced due to the early initiation of the prefetch operation.

Dependencies are inferred from the claim text.