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US 6,246,618 B1Granted
Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsSeiji Yamamoto, Koji Goto, Yasushi Okamoto
Life of this patent
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Abstract
A semiconductor integrated circuit comprises many RAMs, a supplementary RAM, and test/repair control logic which detects a defective RAM out of the multiple RAMs. If a defective RAM is detected, selectors supplement such a defective RAM with the supplementary RAM.
Claims18
A semiconductor integrated circuit comprising:
- a plurality of memories;
- a supplementary memory different from said plurality of memories;
- a first testing unit which performs a first test with respect to each of said plurality of memories to detect whether any of said plurality of memories is defective;
- and
- a supplement control unit which receives a test result of the first test carried out by said first testing unit, and if the test result shows that there is a defective memory in said plurality of memories, replaces the defective memory with said supplementary memory based on a supplement control signal.
2 more elements
A method of memory repair for a semiconductor integrated circuit comprising a plurality of memories and a supplementary memory, comprising
- performing a first test to detect a defective memory among said plurality of memories;
- and
- supplementing with said supplementary memory said defective memory detected among said plurality of memories based on a supplement control signal in accordance with a result of the first test.
A computer readable medium storing instructions which, when executed by a computer, cause the computer to:
- perform a test to detect a defective memory among a plurality of memories;
- and
- supplement with a supplementary memory said defective memory detected among said plurality of memories based on a supplement control signal in accordance with a result of the test.
Dependencies are inferred from the claim text.