Realizing analog-to-digital converter on a digital programmable integrated circuit

A programmable integrated circuit, comprising:

• a plurality of configurable logic blocks;
• a common conductor;
• and
• a plurality of interface cells, each of the interface cells comprising:
• a first pad;
• a second pad;
• a comparator having a first differential input lead, a second differential input lead, and an output lead;
• first coupling means for coupling the first differential input lead to the first pad;
• second coupling means for programmably coupling the second differential input lead to one of the second pad and the common conductor;
• and
• a digital logic element having an input lead, the input lead being couplable to the output lead of the comparator.

A field programmable gate array comprising a plurality of configurable logic blocks and a plurality of interface cells, each of the interface cells comprising:

• a pad;
• a first comparator having a differential input lead and an output lead;
• a node internal to the interface cell;
• means for (i) supplying a digital signal on the pad to the node, or (ii) supplying an analog signal on the pad to the differential input lead of the first comparator such that a digital signal on the output lead of the first comparator is supplied to the node.

In a programmable integrated circuit comprising an array of configurable logic blocks and first and second configurable interface cells, the first and second configurable interface cells being substantially structurally identical to each other, each of the first and second configurable interface cells including a comparator, a method comprising:

• applying a digital signal to the comparator of the first configurable interface cell;
• applying an analog signal to the comparator of the second configurable interface cell;
• and
• using the comparator of the second configurable interface cell to generate part of a multi-bit signal indicating the magnitude of the analog signal.

A programmable integrated circuit, comprising:

• a first bank of configurable interface cells disposed along an edge of the programmable integrated circuit, each interface cell of the first bank comprising a comparator and a pad, the comparator having a first differential input lead and a second differential input lead, the first differential input lead being coupled to the pad;
• a first conductor that extends in a direction substantially parallel to the edge of the programmable integrated circuit, the first conductor being coupled to the second differential input lead of the comparator of each of the comparators of the first bank of configurable interface cells;
• a second bank of configurable interface cells disposed along the edge of the programmable integrated circuit, each interface cell of the second bank comprising a comparator and a pad, the comparator having a first differential input lead and a second differential input lead, the first differential input lead being coupled to the pad;
• and
• a second conductor that extends in a direction substantially parallel to the edge of the programmable integrated circuit, the second conductor being coupled to the second differential input lead of the comparator of each of the comparators of the second bank of configurable interface cells;
• wherein a reference voltage is present on the first conductor, and wherein a digital input signal is received on the pad of the comparator of one of the configurable interface cells of the first bank, and
• wherein an analog input signal is present on the second conductor, and wherein the configurable interface cells of the second bank form a part of an analog-to-digital converter, the analog-to-digital converter converting the analog input signal into a multibit digital value, wherein each of the configurable interface cells of the first bank and each of the configurable interface cells of the second bank has a substantially identical structure.

A programmable integrated circuit, comprising:

• a plurality of configurable logic blocks;
• a common conductor, a reference voltage being present on the common conductor;
• a first interface cell comprising a comparator and a pad, the comparator of the first interface cell comparing a digital signal on the pad to the reference voltage on the common conductor;
• and
• a second interface cell comprising a comparator and a pad, the comparator of the second interface cell being part of an analog-to-digital converter, the analog-to-digital converter outputting a multibit digital value indicative of a magnitude of an analog signal present on the pad of the second interface cell, the first interface cell and the second interface cell being substantially structurally identical.