PMOS low drop-out voltage regulator using non-inverting variable gain stage

A modified Miller compensated voltage regulator comprising:

• a differential amplifier input stage having a first input, a second input, and an output;
• a non-inversion variable gain amplifier stage having an output, a first input connected to a reference voltage, and a second input coupled to the output of the differential amplifier input stage;
• a PMOS output transistor having a source, drain and gate;
• a unity gain buffer coupling the non-inversion variable gain amplifier stage to the gate of the PMOS output transistor;
• and
• a feedback capacitor coupled at a first end to the PMOS output transistor drain, and coupled at a second end to the non-inversion variable gain amplifier stage second input to form a compensation loop;
• wherein the non-inversion variable gain amplifier stage, the unity gain buffer, the PMOS output transistor, and the feedback capacitor are responsive to a changing load current to control a unity gain bandwidth associated with the compensation loop.

A modified Miller compensated voltage regulator comprising:

• an input amplifier stage configured to receive an input reference voltage and further configured to receive a feedback current via a nested Miller compensation capacitor associated with the voltage regulator to generate a displacement current to provide an effective Miller multiplied compensating capacitance;
• a non-inversion variable gain amplifier stage having an output pole associated therewith, the non-inversion variable gain amplifier stage configured to receive the feedback displacement current associated with the nested Miller compensation capacitor such that the pole associated with the output of the non-inversion variable gain amplifier stage is pushed out to a frequency above a Unity Gain Frequency associated with the compensation loop and further configured to generate an amplified displacement current signal therefrom;
• and
• an output amplifier stage having a pole associated therewith, the output amplifier stage configured to receive the amplified displacement current signal such that the pole associated with the output amplifier stage is pushed out to a frequency above the Unity Gain Frequency of the compensation loop thereby rendering the voltage regulator output stage capable of generating a stable regulated output voltage at frequencies in the vicinity of the control loop bandwidth associated with the voltage regulator.

A modified Miller compensated voltage regulator comprising:

• means for generating a feedback current;
• means for generating a displacement current from the feedback current;
• means for amplifying the displacement current such that non-dominant poles associated with the voltage regulator are pushed to frequencies outside the control loop bandwidth of the voltage regulator;
• and
• means for generating output voltage signals having substantially maximized power supply ripple rejection characteristics inside the control loop bandwidth.

A modified Miller compensated voltage regulator comprising:

• a supply voltage node;
• an output voltage node;
• a ground;
• an output power PMOS device having a source connected to the supply voltage node, a drain connected to the output voltage node, and a gate;
• a common source PMOS device having a source connected to the supply voltage node, a gate connected to the gate of the power PMOS device, and a drain;
• a unity gain buffer having a bias input connected to the drain of the common source PMOS device, an output connected to the gate of the power PMOS device, an inverting input connected to the buffer output, and a non-inverting input;
• a non-inversion variable gain amplifier having an output connected to the unity gain buffer non-inverting input, a reference voltage input connected to a ground reference voltage, and a non-inverting input;
• a differential amplifier having a bias input connected to the supply voltage node, an output connected to the non-inverting input of the non-inversion variable gain amplifier, an inverting input connected to a reference voltage, and a non-inverting input;
• a voltage divider network having a first node connected to the power PMOS drain, a second node connected to ground, and a third node connected to the differential amplifier non-inverting input to provide a feedback voltage;
• and
• a compensation capacitor connected at one end to the power PMOS device drain and connected at an opposite end to differential amplifier output.