US 6,242,939 B1 · Superconducting circuit having superconductive circuit device of voltage-type logic and superconductive circuit device of fluxoid-type logic device selectively used therein

Abstract

A superconducting circuit device of a voltage-type logic device is large in current driving capability and, accordingly, electric power consumption; however, the switching speed is not so fast, and a superconducting circuit device of a fluxoid-type logic device is small in current driving capability and, accordingly, the electric power consumption; however the switching speed is faster than that of the superconducting circuit device of the voltage-type logic device, wherein the superconducting circuit device of the voltage-type logic device and the superconducting circuit device of the fluxoid-type logic device are selectively used in a superconducting circuit such as a superconducting random access memory, a superconducting NOR circuit and a superconducting signal converting circuit so as to realize small electric power consumption and high-speed switching action.

Claims19

Dependent claims

A superconducting random access memory comprising:

plural memory cell blocks each including plural random access memory cells and a first peripheral circuit used for selectively accessing data stored in said plural random access memory cells,
said first peripheral circuit having
a decoder circuit formed by using superconducting single flux quantum devices biased with direct current and producing decoded address signals from an address signal, and
a driver circuit formed by using superconducting latching devices biased with alternating current and connected between said decoder circuit and said plural random access memory cells so as to render said plural random access memory cells selectively accessible;
a second peripheral circuit associated with said plural random access memory blocks, and including
a block decoder rendering said plural random access memory blocks selectively accessible, and
plural block driver circuits formed by using superconducting latching devices and connected at least between said block decoder and said plural random access memory blocks for propagating decoded signals from said block decoder to said plural random access memory blocks;
and
signal propagation lines connected between said plural block driver circuits, impedance matching being achieved between said signal propagation lines and said plural block driver circuits.

6 more elements

A superconducting NOR circuit comprising

a superconducting OR circuit including a first output node, plural input nodes respectively supplied with plural input signals and plural superconducting quantum interference devices coupled in series between said first output node and a constant voltage source and magnetically coupled to said plural input nodes, respectively, each of said plural superconducting quantum interference devices including a superconductive loop having at least two Josephson junctions and first inductors,
a bias feed resistor connected between a source of direct bias current and said first output node,
a series combination of a load resistor and a second inductor connected to said first output node, and
a superconducting NOT circuit including an input connected to said series combination and a second output node for producing an output signal representative of the NOR logic between said plural input signals.

1 more element

A superconducting signal converting circuit comprising

a first Josephson junction having a first node connected to a signal input node and a second node connected to a ground terminal and operative in an over-damping state at a first McCumber coefficient equal to or less than 1,
a second Josephson junction having a third node connected a fourth node and a fifth node connected to said ground terminal and operative in an under-damping state at a second McCumber coefficient greater than 1,
a third Josephson junction having a sixth node connected to a signal output node and a seventh node connected to said ground terminal and operative in said under-damping state at said second McCumber coefficient greater than 1,
a series combination of an inductor and a fourth Josephson junction having an eight node connected to said signal input node and a ninth node connected to said fourth node, said fourth Josephson junction being operative in said under-damping state at said second McCumber coefficient greater than 1,
a first resistor having a tenth node connected to said fourth node and an eleventh node connected to a twelfth node,
a second resistor having a thirteenth node connected to said twelfth node and a fourteenth node connected to said signal output node,
a third resistor having a fifteenth node connected to said fourth node and a sixteenth node connected to said output node,
a first bias node supplying a direct bias current to said signal input node, and
a second bias node supplying an alternating bias current to said twelfth node.

6 more elements

Dependencies are inferred from the claim text.

Superconducting circuit having superconductive circuit device of voltage-type logic and superconductive circuit device of fluxoid-type logic device selectively used therein

Life of this patent

Superconducting circuit having superconductive circuit device of voltage-type logic and superconductive circuit device of fluxoid-type logic device selectively used therein

Life of this patent

Abstract

Claims19