Apparatus for dynamically reconfiguring a processor
AssigneeSun Microsystems, Inc.
InventorsRamesh Panwar, Ricky C. Hetherington
Life of this patent
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Abstract
A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise instructions from a number (m) threads. The instructions in each of the m threads are executed on one of the m strands using execution resources at least some of which are shared among the m strands. While the coded instructions comprise instructions from a number (n) threads, the processor is placed in a second configuration having a second number (n) of strands. The instruction are executed in each of the n strands using execution resources at least some of which are shared among the n strands.
Claims8
A processor that executes coded instructions wherein the coded instructions comprise instructions from one or more threads, the processor comprising:
- a processor create unit coupled to said processor to reconfigure the processor as a uniprocessor or in a multiprocessor configuration by specifying a number of virtual processors in response to a processor create instruction;
- a fetch unit coupled to the processor create unit and operative to fetch selected bundles of instructions on a thread-by-thread basis from a memory;
- a marking unit coupled to the fetch unit and operative to receive the instruction bundles from the fetch unit and mark each bundle with a thread identification, wherein each thread has a unique thread identification;
- a dependency checking unit coupled to the fetch unit and operative to determine-dependency between instructions;
- a scheduling unit coupled to the dependency checking unit to receive the marked instructions from the dependency checking unit and operative to pick instructions for execution on a thread-by-thread basis based on results from the dependency checking unit;
- a plurality of architectural register files, each file comprising a plurality of architectural registers;
- at least one execution unit receiving picked instructions from the scheduling unit and computing instruction results from source values in the architectural registers;
- a retirement unit responsive to the at least one execution unit for transferring the instruction results to architectural registers;
- and
- a data cache unit receiving the instruction results and saving the instruction results to a memory.
A computer system comprising:
- a memory;
- a processor coupled to the memory, the processor further comprising:
- a processor create unit coupled to said processor to reconfigure the processor as a uniprocessor or in a multiprocessor configuration by specifying a number of virtual processors in response to a processor create instruction;
- a fetch unit coupled to the processor create unit and operative to fetch selected bundles of instructions on a thread-by-thread basis from a memory;
- a marking unit coupled to the fetch unit and operative to receive the instruction bundles from the fetch unit and mark each bundle with a thread identification, wherein each thread has a unique thread identification;
- a dependency checking unit coupled to the fetch unit and operative to determine dependency between instructions;
- a scheduling unit coupled to the dependency checking unit to receive the marked instructions from the dependency checking unit and operative to pick instructions for execution on a thread-by-thread basis based on results from the dependency checking unit;
- a plurality of architectural register files, each file comprising a plurality of architectural registers;
- at least one execution unit receiving picked instructions from the scheduling unit and computing instruction results from source values in the architectural registers;
- a retirement unit responsive to the at least one execution unit for transferring the instruction results to architectural registers;
- and
- a memory system receiving the instruction results and saving the instruction results to a memory.
A processor that executes coded instructions comprising:
- a processor create unit coupled to said processor to reconfigure the processor as a uniprocessor or in a multiprocessor configuration by specifying a number of virtual processors in response to a processor create instruction;
- an instruction fetch unit responsive to the processor create unit to fetch selected coded instructions on a virtual processor-by virtual processor basis;
- an instruction execution unit coupled to receive the fetched instructions and compute instruction results;
- and
- an instruction retirement unit coupled to place the instruction results in architectural registers associated with each virtual processor.
Dependencies are inferred from the claim text.