System and method for programmably controlling data transfer request rates between data sources and destinations in a data processing system

A method for controlling the flow of data transfer requests during normal system operations of a multiprocessing computing system having a plurality of request sources providing data transfer requests to a plurality of request destinations in accordance with a predetermined request dispatch priority scheme, wherein each data transfer request is a request for an addressed one of the request destinations to supply a data segment to a respective one of the request sources, the method comprising:

• periodically performing first data transfer operations between a first request source and a targeted request destination;
• initiating a second data transfer operation between a second request source and the targeted request destination, wherein the second data transfer operation is subject to a response timeout limitation;
• suspending the first data transfer operations for a user-defined period upon recognition of initiation of the second data transfer operation;
• enabling the second data transfer operations during the user-defined period;
• and
• upon expiration of the user-defined period, enabling both the first data transfer operations and the second data transfer operations in accordance with the predetermined request dispatch priority scheme.

A method for controlling the flow of data transfer requests during offline testing of a multiprocessing computing system having a plurality of request sources capable of providing data transfer requests to a plurality of request destinations in accordance with a predetermined request dispatch priority scheme, the multiprocessing computing system including a main storage unit having a plurality of data transfer queues that operate in parallel to temporarily store the data transfer requests from the request sources to the request destinations, the method comprising:

• selecting a first one of the plurality of data transfer queues to initialize the memory in the main storage unit;
• loading a number of known data transfer requests into second ones of the plurality of data transfer queues, wherein the second ones of the data transfer queues comprise at least one of the remaining ones of the data transfer queues not selected to initialize the memory;
• prohibiting data transfer operations from the second data transfer queues for a user-defined period;
• executing a memory initialization sequence via the first data transfer queue;
• and
• enabling the data transfer operations from the second data transfer queues upon expiration of the user-defined period.

A data transfer request interface circuit for use in a multiprocessing computing system having at least one request source to provide data transfer requests to at least one request destination, the interface circuit comprising:

• a queuing circuit coupled to each of the request sources to receive and temporarily store the data transfer requests;
• a priority logic circuit coupled to the queuing circuit to prioritize a sequence by which the stored data transfer requests are output from the queuing circuit in accordance with a predetermined priority algorithm;
• a masking register coupled to the priority logic circuit to mask predetermined ones of the stored data transfer requests from being considered by the priority logic circuit in response to a masking signal pattern provided to the masking register, thereby retaining the predetermined ones of the stored data transfer requests in the queuing circuit while allowing remaining ones of the stored data transfer requests to be prioritized and output from the queuing circuit;
• and
• a configurable request flow controller coupled to the masking register to generate the masking signal pattern in response to user-defined parameters, wherein the user-defined parameters define at least which of the stored data transfer requests are to be masked by the masking register, and the duration to which the masking signal pattern is to be sustained.

A data transfer request interface circuit for use in a multiprocessing computing system having at least one request source to provide data transfer requests to at least one request destination, the interface circuit comprising:

• queuing means coupled to each of the request sources for receiving and storing the data transfer requests;
• request prioritization means coupled to the queuing means for prioritizing a delivery order of the stored data transfer requests from the queuing means;
• request masking means coupled to the request prioritization means for disabling prioritization and delivery of predetermined ones of the stored data transfer requests in response to a masking signal pattern, thereby retaining the predetermined ones of the stored data transfer requests in the queuing means while allowing remaining ones of the stored data transfer requests to be prioritized and output by the queuing means;
• flow control means coupled to the request masking means for generating the masking signal pattern in response to user-defined parameters, wherein the user-defined parameters define at least which of the stored data transfer requests are to be disabled from delivery, and the duration to which the masking signal pattern is to be sustained.