Synchronous type semiconductor memory system with less power consumption

A method of carrying out power saving in a synchronous type dynamic random access memory (SDRAM) comprising:

• generating a first power down signal and a second power down signal based on a clock enable signal, an external clock signal, a signal specific to said SDRAM and a write burst signal, wherein said first power down signal is inactive during a predetermined time period synchronous with said specific signal, and said second power down signal is inactive during a time period during which a write burst signal is supplied;
• generating a control signal based on a command signal when said first power down signal is inactive;
• generating an internal address signal from an external address signal for accessing a memory cell array section based on said control signal when said first power down signal is inactive;
• generating an internal write data signal from an external write data signal for accessing said memory cell array section based on said control signal when said second power down signal is inactive;
• and
• generating an external read data signal from an internal read data signal read out from said memory cell array section based on said control signal.

A memory (SDRAM) system comprising:

• a plurality of synchronous type dynamic random access memories (SDRAMs), signals specific to said SDRAMs being supplied to said SDRAMs;
• a bus connected to said plurality of SDRAMs;
• a control unit transferring an external clock enable signal, an external clock signal, an external command signal, an external address signal and a data signal in common to said plurality of synchronous type dynamic random access memories via said bus and respectively transferring said specific signals to said plurality of synchronous type dynamic random access memories, and
• wherein each of said plurality of synchronous type dynamic random access memories comprises:
• a memory cell array section having an address decoder section and a sense amplifier section;
• a power down signal generating section generating a first power down signal and a second power down signal based on said external clock enable signal, said external clock signal, said specific signal and a write burst signal, wherein said first power down signal is inactive during a predetermined time period synchronous with said specific signal, and said second power down signal is inactive during a time period during which said write burst signal is supplied;
• a control signal generating section generating a control signal based on a command signal when said first power down signal is inactive;
• and
• an accessing section accessing said memory cell array section based on said external address signal and said external data signal in response to said control signal when said first power down signal is inactive in a read mode and said second power down signals is inactive in a write mode.