Multiple bank simultaneous operation for a flash memory

An N-tuple bank simultaneous operation flash memory, wherein for the duration of a read operation at the Nth bank, a write operation can only be performed on any one of the other N-1 banks, and wherein for the duration of a write operation at the Nth bank is accessed for a write operation, a read operation can only be performed on any one of the other N-1 banks, the memory comprising:

• a control logic circuit to generate N read select signals and N write select signals;
• address buffer circuitry;
• N localized bank circuitries, wherein the circuitries 1 through N-1 comprise N-1 respective banks of core memory cells, and wherein the Nth circuitry comprises:
• an Nth bank of core memory cells;
• address selection circuitry, wherein the address selection circuitry is responsive to the Nth read select signal and the Nth write select signal;
• a write operation control circuit, wherein the write operation control circuit is responsive to the Nth write select signal;
• a write data bus, wherein the write data bus is responsive to the Nth write select signal;
• and
• a read data bus, wherein the read data bus is responsive to the Nth read select signal.

In a memory, a method of performing simultaneous writing and reading of data within a multiple bank flash memory, the method comprising:

• providing a first portion of a write address and a first portion of a read address to N address selection circuits corresponding to N banks of core memory cells;
• providing a second portion of the write address to a control logic circuit, the second portion of the write address defining one bank for a write operation;
• providing a second portion of the read address to a control logic circuit, the second portion of the read address defining one bank for a read operation;
• providing one of N write select signals from the control logic circuit to each bank of the N banks for a write operation;
• providing one of N read select signals from the control logic circuit to select another bank of the N banks for a read operation;
• gating the first portions of the write and read addresses to the N banks with the respective N write select signals and the respective N read select signals;
• and
• gating the data that are accessed at write and read address sites in the N banks by the first portions of the write and read addresses to data output and verification circuitry with the respective N write select signals and the respective N read select signals.