DRAM content addressable memory using part of the content as an address

A content addressable memory device comprising:

• a memory array having memory cells organized into a plurality of rows;
• a row decoder coupled to said memory array, said row decoder using a first portion of a desired content as a row address for said memory array and activating a row of memory cells within said memory array based on the row address;
• and
• a compare logic circuit coupled to said memory array, said compare logic circuit comparing stored content of said activated row of memory cells with a second portion of the desired content.

A content addressable memory device comprising:

• a memory array having memory cells organized into a plurality of rows;
• a row decoder coupled to said memory array, said row decoder using a row address computed from a desired content to activate a row of memory cells within said memory array based on the row address;
• and
• a compare logic circuit coupled to said memory array, said compare logic circuit comparing stored content of said activated row of memory cells with a remainder of the desired content.

A processor based system comprising:

• a processor;
• and
• a memory device coupled to said processor, said memory device comprising:
• a memory array having memory cells organized into a plurality of rows;
• a row decoder coupled to said memory array, said row decoder using a first portion of a desired content as a row address for said memory device and activating a row of memory cells within said memory array based on the row address;
• and
• a compare logic circuit coupled to said memory array, said compare logic circuit comparing stored content of said activated row of memory cells with a second portion of the desired content.