Low-pin-count chip package and manufacturing method thereof
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorChun Hung Lin
Life of this patent
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Abstract
A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is formed over the semiconductor chip, the die pad and the connection pads in a manner that a potion of the die pad and a portion of each connection pad extend outward from the bottom of the package body. The present invention further provides a novel method of producing the low-pin-count chip package described above.
Claims8
A method of making a low-pin-count chip package comprising the steps of:
- providing a metal carrier plate having opposing upper and lower surfaces, the upper surface of the metal carrier plate having a central bulge for receiving a semiconductor chip and a plurality of peripheral bulges arranged at the periphery of the central bulge, the upper surfaces of the central bulge and the peripheral bulges having a first metal coating formed thereon, the lower surface of the metal carrier plate having a second metal coating formed corresponding to the first metal coating;
- attaching a semiconductor chip onto the central bulge of the metal carrier plate;
- electrically coupling the semiconductor chip to the peripheral bulges of the metal carrier plate;
- forming a package body over the semiconductor chip and the metal carrier plate;
- and
- etching areas on the lower surface of the metal carrier plate without protection of the second metal coating such that the central bulge and each of the peripheral bulges are separated from one another so as to form a die pad and a plurality of connection pads wherein a portion of the die pad and a portion of each connection pad extend outward from the bottom of the package body.
A method of making a low-pin-count chip package comprising the steps of:
- providing a metal carrier plate having opposing upper and lower surfaces, the upper surface of the metal carrier plate having a die receiving area and a plurality of peripheral bulges arranged at the periphery of the die receiving area, the upper surfaces of the peripheral bulges having a first metal coating formed thereon, the lower surface of the metal carrier plate having a second metal coating formed corresponding to the first metal coating;
- attaching a semiconductor chip onto the die receiving area of the metal carrier plate;
- electrically coupling the semiconductor chip to the peripheral bulges of the metal carrier plate;
- forming a package body over the semiconductor chip and the metal carrier plate;
- and
- etching areas on the lower surface of the metal carrier plate without protection of the second metal coating such that the peripheral bulges are separated from one another so as to form a plurality of connection pads, wherein a portion of each connection pad extends outward from the bottom of the package body.
Dependencies are inferred from the claim text.