Fractional-N divider using a delta-sigma modulator

A fractional-N divider for use in a fractional-N frequency synthesizer, the fractional-N divider comprising:

• a. a dead zone quantizer, the dead zone quantizer responding to a high resolution digital word and the dead zone quantizer providing a first low resolution digital word;
• b. an error shaping filter, the error shaping filter responding to a fixed-point binary input signal, the first low resolution digital word and a clock signal and the error shaping filter providing the high resolution digital word, wherein the error shaping filter comprises:
• i. a first filter, the first filter responding to the first low resolution digital word and the clock signal and the first filter providing a loop stabilizing signal, where in first filter comprises:
• (1) a first storage register, the first storage register responding to the first low resolution digital word and the clock signal and the first storage register providing a first lookup table input signal;
• (2) a second storage register, the second storage register responding to the first lookup table input signal and the clock signal and the second storage register providing a second lookup table input signal;
• and
• (3) a lookup table, the lookup table responding to the first lookup table input signal, the second lookup table signal and the fixed point binary input and the lookup table providing a lookup table output signal;
• ii. a second summer, the second summer responding to the fixed-point binary input and the loop stabilizing signal and the second summer providing a difference signal proportional to the difference between the fixed-point binary input and the loop stabilizing signal;
• iii. a second filter, the second filter responding to the difference signal and the clock signal and the second filter providing the high resolution digital word, wherein the second filter comprises:
• (1) a first digital adder, the first digital adder responding to the lookup table output signal, the fixed point binary input and a third register output signal and the first digital adder providing a first digital adder output signal;
• (2) a second digital adder, the second digital adder responding to the first digital adder output signal and a fourth register output signal and the second digital adder providing the high resolution digital word;
• (3) a third register, the third register responding to the clock signal and the first digital adder output signal and the third register providing the third register output signal;
• and
• (4) a fourth register, the fourth register responding to the clock and the second digital adder output signal and the fourth register providing the second register output signal;
• c. a programmable divider, the programmable divider responding to a synthesizer output signal and the control signal and the programmable divider providing a divided signal;
• d. a filter for contiguous tuning means, the filter responding to the first low resolution digital word and the clock signal and the filter providing a filtered first low resolution digital word;
• e. a first summer, the first summer responding to the filtered first low resolution digital word and a programmed base value and the first summer providing a control signal;
• and
• f. a residual error compensator, the residual error compensator responding to the first low resolution digital word and the high resolution digital word and the clock signal and the residual error compensator providing a higher order, noise shaped first low resolution digital word, wherein the residual error compensator comprises:
• i. a third summer, the third summer responding to the high resolution digital word and the first low resolution digital word and the third summer providing an error signal proportional to the difference between the high resolution digital word and the first low resolution digital word;
• ii. a delta-sigma modulator, the delta-sigma modulator responding to the error signal and the clock signal and the delta-sigma modulator providing a second low resolution digital word;
• iii. a fourth filter, the fourth filter responding to the second low resolution digital word and the clock signal and the fourth filter providing a filtered second low resolution digital word;
• and
• iv. a fourth summer, the fourth summer responding to the filtered second low resolution digital word and the first low resolution digital word and the fourth summer providing the higher order, noise shaped first low resolution digital word.