Apparatus and method for a fast locking phase locked loop
AssigneeNational Semiconductor Corporation
InventorChristian Olgaard
Life of this patent
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Abstract
A control circuit for causing a phase lock loop (PLL) frequency synthesizer to achieve a fast phase lock time while also providing improved loop performance during normal phase locked operation. The phase locking time of the PLL is minimized by initially configuring the PLL to operate in a fractional mode with high frequency signals presented to the inputs of the loop phase detector, thereby producing a fast phase lock time. Once the PLL has achieved phase lock, its operation mode is transitioned to either an integer mode or an open loop mode without loss of phase lock, thus causing lower frequency signals or no signals, respectively, to be presented to the inputs of the loop phase detector and thereby significantly reducing spurious signal tones.
Claims33
An apparatus including a dual mode control circuit for a phase lock loop (PLL), comprising:
- a reference signal frequency divider circuit configured to couple to a PLL and receive at least one reference divider control signal and in accordance therewith receive and frequency divide an input reference signal having an input reference signal frequency and in accordance therewith provide one or more divided reference signals having one or more divided reference signal frequencies and phases;
- a feedback signal frequency divider circuit configured to couple to said PLL and receive at least one feedback divider control signal and in accordance therewith receive and frequency divide a PLL feedback signal having a PLL feedback signal frequency and in accordance therewith provide one or more divided feedback signals having one or more divided feedback signal frequencies and phases;
- and
- a control circuit, coupled to said reference and feedback signal frequency divider circuits, configured to couple to said PLL, receive a PLL lock signal from said PLL and receive and process one of said one or more divided feedback signals and in accordance therewith provide said at least one reference divider control signal and said at least one feedback divider control signal;
- wherein said control circuit, in accordance with said PLL lock signal, and said reference and feedback signal frequency divider circuits, in accordance with said at least one reference divider control signal and said at least one feedback divider control signal, transition between first and second circuit operation modes when
- said PLL lock signal indicates that said PLL has transitioned between unlocked and phase locked states of operation, and
- said processing of said one of said one or more divided feedback signals indicates that a phase difference between said one of said one or more divided feedback signal phases and a desired signal phase transitions between outside and inside of a predetermined phase difference range.
A method of controlling a phase lock loop (PLL) in accordance with dual PLL operation modes, comprising the steps of:
- coupling to a PLL;
- receiving from said PLL a PLL feedback signal having a PLL feedback signal frequency;
- receiving at least one reference divider control signal and in accordance therewith receiving and frequency dividing an input reference signal having an input reference signal frequency and in accordance therewith generating one or more divided reference signals having one or more divided reference signal frequencies and phases;
- receiving at least one feedback divider control signal and in accordance therewith frequency dividing said PLL feedback signal and in accordance therewith generating one or more divided feedback signals having one or more divided feedback signal frequencies and phases;
- receiving a PLL lock signal from said PLL and receiving and processing one of said one or more divided feedback signals and in accordance therewith generating said at least one reference divider control signal and said at least one feedback divider control signal;
- and
- transitioning between first and second operation modes in accordance with said PLL lock signal, said at least one reference divider control signal and said at least one feedback divider control signal when
- said PLL lock signal indicates that said PLL has transitioned between unlocked and phase locked states of operation, and
- said processing of said one of said one or more divided feedback signals indicates that a phase difference between said one of said one or more divided feedback signal phases and a desired signal phase transitions between outside and inside of a predetermined phase difference range.
Dependencies are inferred from the claim text.