Line receiver circuit with large common mode range for differential input signals

A line receiver circuit for receiving differential digital signals from a symmetrical transmission line, having a pair of differential input terminals for connection with said transmission line and having an output for outputting data signals corresponding to signals received via said transmission line, said line receiver circuit comprising:

• a first differential input stage having a first pair of differential inputs connected to receive input signals from said pair of differential input terminals;
• said first input stage being adapted to receive and process differential signals having a common mode voltage within a first lower common mode voltage range;
• a second differential input stage having a second pair of differential inputs connected to receive input signals from said pair of differential input terminals;
• said second input stage being adapted to receive and process differential signals having a common mode voltage within a second higher common mode voltage range, wherein the second higher common mode voltage range is at least partially greater or higher than the first lower common mode voltage range of the first input stage;
• a circuit for combining output signals provided by said first differential input stage and output signals provided by said second differential input stage;
• a circuit for detecting an operating condition of said first input stage which operating condition depends on a common mode input voltage at said inputs of said first input stage, wherein the detected operating condition indicates when the first input stage reaches an upper limit of the first lower common mode voltage range;
• and
• a circuit for selectively activating said second input stage depending on said detected operating condition of said first input stage so that the second input stage is active when said circuit for detecting detects that the common mode input voltage reaches the upper limit of the first lower common mode voltage range of the first input stage, so that operation of the second input stage for the second higher common mode voltage is inhibited until the upper limit of the first input stage for the lower common mode voltage range has been reached.

A method of operating a line receiver circuit for receiving differential digital signals from a symmetrical transmission line, the line receiver circuit having a pair of differential input terminals for connection with said transmission line and having an output for outputting data signals corresponding to signals received via said transmission line, said method comprising:

• providing the line receiver circuit with a first differential input stage having a first pair of differential inputs connected to receive input signals from said pair of differential input terminals, and a second differential input stage having a second pair of differential inputs connected to receive input signals from said pair of differential input terminals;
• the first input stage receiving and processing differential signals having a common mode voltage within a first lower common mode voltage range;
• the second input stage receiving and processing differential signals having a common mode voltage within a second higher common mode voltage range, wherein the second higher common mode voltage range is at least partially greater or higher than the first lower common mode voltage range;
• combining output signals provided by said first differential input stage and output signals provided by said second differential input stage;
• detecting an operating condition of said first input stage which operating condition depends on a common mode input voltage at said inputs of said first input stage, wherein the detected operating condition indicates when the first input stage reaches an upper limit of the first lower common mode voltage range;
• and
• selectively activating the second input stage depending on said detected operating condition of said first input stage so that the second input stage is active when it is detected that the common mode input voltage reaches the upper limit of the first lower common mode voltage range of the first input stage, so that operation of the second input stage for the second higher common mode voltage is inhibited until the upper limit of the first input stage for the lower common mode voltage range has been reached.