Programmable logic integrated circuit devices with low voltage differential signaling capabilities

A programmable logic device having programmable logic circuitry comprising:

• a pair of interface terminals configured for use in making connections to circuitry that is external to the programmable logic device;
• LVDS buffer circuitry connected to both of the interface terminals and configured to exchange with the interface terminals a pair of signals which are respectively associated with the pair of interface terminals and which differ from one another in voltage in order to represent information in accordance with an LVDS standard;
• and
• programmable function control circuitry configured to selectively enable the LVDS buffer circuitry.

A programmable logic device having programmable logic circuitry comprising:

• a pair of interface terminals configured for use in making connections to circuitry that is external to the programmable logic device;
• LVDS buffer circuitry connected to both of the interface terminals and configured to exchange with the interface terminals a pair of signals which are respectively associated with the pair of interface terminals and which differ from one another in voltage in order to represent information in accordance with an LVDS standard;
• and
• single-conductor signaling buffer circuitry connected to one of the interface terminals and configured to exchange with the one of the interface terminals a single signal having voltages which represent data in accordance with a single-conductor signaling standard.

A programmable logic device having programmable logic circuitry comprising:

• a pair of interface terminals configured for use in making connections to circuitry that is external to the programmable logic device;
• LVDS buffer circuitry connected to both of the interface terminals and configured to exchange with the interface terminals a pair of signals which are respectively associated with the pair of interface terminals and which differ from one another in voltage in order to represent information in accordance with an LVDS standard, wherein the LVDS buffer circuitry is further configured to receive from the logic circuitry of the device a single input signal indicative of the information and to produce the pair of signals indicative of the information for application to the interface terminals;
• and wherein the LVDS buffer circuitry comprises:
• a source of relatively high voltage;
• a source of relatively low voltage;
• differential output switching circuitry configured to produce the pair of signals in response to the single input signal;
• first resistor circuitry connected in series between the source of relatively high voltage and the differential output switching circuitry;
• and
• second resistor circuitry connected in series between the differential output switching circuitry and the source of relatively low voltage, connections between the sources, the differential output switching circuitry, and the first and second resistor circuitries being such that when the circuitry that is external to the device is connected to the interface terminals, current flows in series from the source of relatively high voltage through the first resistor circuitry, through the circuitry that is external to the device, through the second resistor circuitry, to the source of relatively low voltage.

A digital processing system comprising:

• processing circuitry;
• a memory coupled to the processing circuitry;
• and
• a programmable logic device coupled to the processing circuitry and the memory, wherein the programmable logic device includes LVDS buffer circuitry connected to a pair of interface terminals and configured to exchange with the interface terminals a pair of signals which are respectively associated with the pair of interface terminals and which differ from one another in voltage in order to represent information in accordance with an LVDS standard.