Method for fabricating stackable chip scale semiconductor package

A method for fabricating a semiconductor package comprising:

• providing a silicon substrate comprising a first surface and an opposing second surface;
• laser machining a via through the substrate from the first surface to the second surface;
• etching the via;
• forming an insulating layer in the via;
• at least partially filling the via with a conductive material to form a conductive via;
• forming a first contact on the first surface in electrical communication with the conductive via;
• forming a second contact on the second surface in electrical communication with the conductive via, the second contact and the first contact having a mating configuration;
• and
• mounting a die to the substrate in electrical communication with the first contact or the second contact.

A method for fabricating a semiconductor package comprising:

• providing a substrate having a first surface and an opposing second surface;
• forming a conductive via through the substrate from the first surface to the second surface by laser machining a via and at least partially filling the via with a conductive material;
• forming a first contact on the first surface in electrical communication with the conductive via;
• forming a second contact on the second surface in electrical communication with the conductive via;
• mounting a die to the substrate in electrical communication with the first contact or the second contact;
• and
• stacking the substrate on a second substrate, the second substrate having a third contact in electrical communication with a second die on the second substrate, the third contact substantially identical to the first contact and bonded to the second contact.

A method for fabricating a semiconductor package comprising:

• providing a silicon substrate having a first surface and an opposing second surface;
• laser machining a plurality of vias in the substrate extending from the first surface to the second surface;
• etching the vias;
• depositing a conductive material within the vias to form conductive vias;
• forming first contacts on the first substrate in electrical communication with the conductive vias;
• forming second contacts on the second substrate in electrical communication with the conductive vias, the second contacts configured to retain and electrically engage the first contacts;
• mounting a die to the substrate;
• and
• forming electrical paths between the die and the first contacts or the second contacts.

A method for fabricating a semiconductor package comprising:

• providing a first wafer and a second wafer;
• forming a plurality of packages on the first wafer and the second wafer, each package including a substrate comprising a portion of the first wafer or the second wafer, and a die in electrical communication with a plurality of first contacts on a first side of the substrate, and with a plurality of second contacts on a second side of the substrate;
• stacking the first wafer to the second wafer with selected first contacts on the first wafer in electrical communication with selected second contacts on the second wafer;
• and
• cutting the first wafer and the second wafer to form a plurality of stacked packages.

A method for fabricating a semiconductor package comprising:

• providing a first package comprising a first contact on a first surface thereof, and a second contact on a second surface thereof, and a conductive via electrically connecting the first contact to the second contact;
• providing a second package substantially identical to the first package and with the second contact on the second package configured to retain and electrically engage the first contact on the first package;
• and
• stacking the first package on the second package with the second contact on the second package retaining and electrically engaging the first contact on the first package.