Self-checked, lock step processor pairs

A processor unit, comprising:

• first and second processor elements operating in lock-step synchronism with each other to execute each instruction of an instruction stream, and to periodically produce identical N-bit data words comprising first and second portions, at substantially the same moment in time;
• a memory for storing the N-bit data words;
• a first interface unit coupling the first processor element to the memory to create an M-bit error code from N-bit data words received from the first processor and to communicate the first portion for storage in the memory in associate with a first part of the M-bit error code;
• a second interface unit coupling the second processor element to the memory to create the M-bit error code from N-bit data words received from the second processor to communicate the second portion for storage in the memory in associate with a second part of the M-bit error code;
• and
• the first and second interface units each including an error circuit for receiving N-bit data words from memory together with the associated M-bit error code to check the N-bit data word for errors.

In a data processing system having first and second data processor elements operating in substantially lock-step synchronism to sequential execute an identical series of instructions, instruction by instruction, to each periodically produce, at substantially the same time, N-bit data elements, each N-bit data element have first and second portions, the data processing system having a memory for storing the N-bit data elements;

• a method for checking operation of the first and second data processor elements, including the steps of:
• communicating the first portion of the N-bit data element from the first data processor element to the memory for storage;
• communicating the second portion of the N-bit data element from the second data processor element to the memory for storage in association with the corresponding first portion;
• and
• comparing the first portion and second portions of each of the N-bit data words from the first data processor element with the first and second portions of the corresponding N-bit data words from the second data processor element;
• and
• producing an error indication when a miscompare is detected.