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AssigneeMicron Technology, Inc.
InventorsRay Beffa, Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud, William K. Waller
Estimating the term…
A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.
A system for stress testing a memory integrated circuit die, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, one of the word lines and the common node, the system comprising:
A system for stress testing a memory integrated circuit die, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines and a sequence of word lines which includes a pair of adjacent word lines, the pair of adjacent word lines including a first word line and a second word line, the plurality of memory cells having a common node and a storage node, the system comprising:
A system for stressing insulation in a memory integrated circuit die, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines and a sequence of word lines which includes a pair of adjacent word lines, the plurality of memory cells having a common node and a storage node, the system comprising:
A system for stress testing a memory integrated circuit die, the system comprising:
A system for stress testing a memory integrated circuit die, the system comprising:
A system for stressing insulation in a memory integrated circuit die, the system comprising:
Dependencies are inferred from the claim text.