Method of designing a constraint-driven integrated circuit layout

A method for designing an integrated circuit layout by using a computer, based upon the selection of cells from a cell library, comprising the steps of:

• (a) designating a plurality of buckets in the integrated circuit layout so that at least some of the cells are assigned in initial placements in the buckets;
• (b) connecting a plurality of global routes having net lengths based upon the initial placements of the cells of step (a);
• (c) performing track routing to fix the position of each of the global routes of step (b);
• (d) performing detailed placement by placing additional cells in the buckets of step (a) after the fixing step (c) so that positions of selected cells are fixed within each of the buckets on the integrated circuit layout;
• and
• (e) placing detailed routes to connect at least some of the additional cells together in one of the buckets.

A method for designing an integrated circuit layout, comprising the steps of:

• (a) placing a first plurality of cells in initial positions designated by buckets;
• (b) forming a plurality of global routes based upon the designated initial positions of the first plurality of cells of step (a);
• (c) performing track routing to fix the positions of the global routes of step (b);
• (d) performing detailed placement by placing a second plurality of cells based upon the positions of the global routes of step (c) such that the positions of all selected cells are fixed within the buckets designated on the integrated circuit layout;
• and
• (e) placing a plurality of detailed routes to complete the integrated circuit layout.

An integrated circuit layout formed on a chip layout comprising:

• a plurality of selected cells;
• global routes for coupling the selected cells together, the global routes having been set in position by a track routing process;
• detailed routes for coupling the global routes to the selected cells;
• and
• a routing space formed in the chip layout for permitting routing completion of the integrated circuit layout;
• wherein the cells are fixed within buckets on the integrated circuit layout by a detailed placement process.

A timing-based integrated circuit layout formed on a chip layout comprising:

• a plurality of cells;
• timing-based global routes for coupling at least some of the cells together, the timing-based global routes being set in position by track routing so as to satisfy timing requirements of the integrated circuit layout;
• and
• detailed routes for coupling the timing-based global routes to at least some of the cells, the at least some of the cells having been fixed in position within buckets designated on the integrated circuit layout by a detailed placement process.

An automated method for satisfying the timing requirements of an integrated circuit layout on a chip layout, comprising the steps of:

• (a) placing a first selected plurality of cells in approximate positions in the chip layout;
• (b) selecting global routes for coupling the first selected plurality of cells together;
• (c) setting the positions of the global routes of step (b) using a track routing process such that a timing parameter of each of the global routes satisfies the timing requirements of the integrated circuit layout;
• and
• (d) placing a second selected plurality of cells based upon the positions of the global routes of step (c) using a detailed placement process such that the positions of selected cells are fixed within each of buckets designated on the integrated circuit layout.

An automated method for achieving routing completion in an integrated circuit layout, comprising the steps of:

• (a) providing a first plurality of cells in approximate positions so that the cells are used to implement the integrated circuit layout;
• (b) placing a plurality of global routes for coupling the first plurality of cells;
• (c) fixing the positions of the global routes using a track routing process;
• (d) placing a second plurality of cells based upon the positions of the global routes of step (c);
• (e) performing detailed routing for coupling the second plurality of cells together and to the global routes;
• and
• (f) performing routing completion so as to form the integrated circuit layout such that positions of all selected cells are fixed within buckets on the integrated circuit layout.

An automated method for designing an integrated circuit layout with a computer, based upon an electronic circuit description and by using a cell library containing a selected plurality of cells, comprising the steps of:

• (a) based upon a portion of a computer program that contains a sequence of instructions, assigning each of the cells to one of a plurality of buckets designated on the integrated circuit layout, each of the cells being connected to one of the other cells based upon the electronic circuit description input to the computer;
• (b) performing global routing to connect at least some of the selected cells of step (a) together such that global routes are formed to provide net topology information;
• (c) performing track routing which sets the position of each of the global routes;
• (d) performing detailed placement such that the positions of all selected cells are fixed within each of the buckets designated on the integrated circuit layout;
• and
• (e) performing detailed routing such that detailed routes are formed to complete the integrated circuit layout.

A automated method for designing an integrated circuit layout by using a computer and based upon an electronic circuit description, comprising the steps of:

• (a) using a portion of a computer program that contains a sequence of instructions, placing a first plurality of cells in designated initial positions;
• (b) forming a plurality of global routes based upon the designated initial positions of the first plurality of cells of step (a);
• (c) performing track routing to fix the positions of the global routes of step (b);
• (d) performing detailed placement on a second plurality of cells based upon the positions of the global routes of step (c) such that positions of all selected cells are fixed in each of buckets designated on the integrated circuit layout;
• and
• (e) placing a plurality of detailed routes to complete the integrated circuit layout.