Memory refresh control system

A memory system comprising:

• a cross-bar switch;
• a plurality of interleaved memory modules, each memory module comprising interleaved memory arrays and a bus interface unit, said bus interface unit providing a connection to said cross-bar switch;
• said memory arrays each comprising interleaved memory ranks where each memory rank is assigned a unique physical rank number (PRN), said memory ranks comprising a plurality of SDRAMs;
• an arbiter connected to said cross-bar switch and to said memory modules, said arbiter controlling access to the memory modules by configuring the cross-bar switch, said arbiter also broadcasting a refresh command to all memory modules and restricting access to a memory rank being refreshed;
• and
• respective refresh registers associated with the arbiter and memory modules which count by incrementing at intervals of a pre-programmed number of clock cycles, wherein the SDRAMs in a particular memory rank on a memory module are triggered to an auto-refresh cycle when the refresh register associated with the memory module matches the PRN of said memory rank, the refresh register associated with the arbiter identifying the memory rank being refreshed thereby allowing the arbiter to restrict access to that memory rank.

In a memory system, a method of refresh scheduling, comprising:

• controlling, with an arbiter, access to a plurality of memory units, said arbiter and memory units having associated refresh registers;
• sequencing each of said refresh registers, independently of the other refresh registers, through memory unit identifiers such that at any given time, all of the refresh registers identify the same memory unit;
• and
• triggering a refresh to a memory unit when a refresh register associated with the memory unit has a designated value, said arbiter using its associated refresh register to identify the memory unit being refreshed to restrict access to that memory unit.

In a memory system, a method of refresh scheduling, comprising:

• interleaving a plurality of memory modules, each memory module comprising interleaved memory arrays, each memory array comprising interleaved memory ranks, each memory rank comprising memory devices requiring periodic refresh;
• controlling, with an arbiter, access to said memory ranks by configuring a cross-bar switch;
• broadcasting a refresh signal to all memory modules;
• counting, upon said broadcast of said refresh signal, by incrementing refresh registers associated respectively with said arbiter and with each of said memory modules, said incrementing being performed at a pre-programmed rate;
• triggering the memory devices in a particular memory rank to an auto-refresh cycle when a refresh register associated with a memory module matches the PRN associated with said memory rank;
• and
• restricting access to the memory rank being refreshed by reference to the refresh register associated with said arbiter.

A memory system comprising:

• a plurality of memory units;
• arbitration means for controlling access to the memory units and restricting access to a memory unit being refreshed;
• ad
• plural sequencing means for sequencing through memory unit identifiers, a sequencing means associated with each memory unit, each sequencing means sequencing independently of the others, each memory unit being triggered to a refresh when said sequencing means has a designated value, said arbitration means referencing a sequencing means to identify the memory unit being refreshed, thereby restricting access to that memory unit.