Method and apparatus for optimizing the path of a physical wire
AssigneeInternational Business Machines Corporation
InventorsToshiyuki Hama, Hiroaki Etoh
Life of this patent
Estimating the term…
Abstract
A method and apparatus for transforming a topological wire route to a physical wire route is described where the topological wire is a connected route having only a topological position determined with respect to terminals or obstacles. A topological wire is first selected and then obstacles which sight the selected wire are identified. A fan with a radius that is a predetermined number times a minimum space is then set to the identified obstacle as a forbidden region. A minimum space must be left between the selected wire and the identified obstacle. Finally, a shortest route is detected so that it does not pass through the forbidden region, and the route of the physical wire on the board is determined with the shortest route.
Claims22
A method for transforming a topological wire route to a physical wire route on a printed circuit board, said method comprising the steps of:
- selecting a topological wire;
- identifying obstacles on both sides of said topological wire which sight said selected topological wire;
- determining a region about each of said identified obstacles;
- and
- determining a route of a physical wire between said obstacles without passing through said regions, said physical wire corresponding to said selected topological wire.
A method for transforming a topological wire route to a physical wire route on a printed circuit board, said method comprises the steps of:
- specifying a first factor by which surplus space on said printed circuit board is allocated to enlargement of wire width and second factor by which the surplus space is allocated to enlargement of wire spacing;
- identifying wires which cross a critical cut between an obstacle and another obstacle and lie between a selected topological wire and said obstacle;
- determining for each of said identified wires a multiplicity of upper limits of wire width enlargement ratios and wire spacing enlargement ratios relative to a multiplicity of obstacles;
- enlarging widths of each of said identified wires based on the lowest upper limit of said wire width enlargement ratios relative to the respective obstacle;
- enlarging wire spacings between each of said identified wires based on the lowest upper limit of wire spacing enlargement ratios relative to the respective obstacle;
- and
- adding the enlarged wire widths and the enlarged wire spacings to determine said enlarged region about said first obstacle.
An apparatus for transforming a topological wire route to a physical wire route on a circuit board, said apparatus comprising:
- means for selecting a topological wire;
- means for identifying obstacles on both sides of said topological wire which sight said selected topological wire;
- means for determining a region about each of said identified obstacles;
- and
- means for determining a route of a physical wire between said obstacles without passing through said regions, said physical wire corresponding to said selected topological wire.
An apparatus for transforming a topological wire route to a physical wire route on a printed circuit board, said apparatus comprising:
- means for specifying a first factor by which surplus space on said board is allocated to enlargement of wire width and a second factor by which the surplus space is allocated to enlargement of wire spacing;
- means for identifying wires which cross a critical cut between one obstacle and another obstacle and lie between an identified topological wire and said one obstacle;
- means for determining for each of said identified wires a multiplicity of upper limits of wire width enlargement ratios and wire spacing enlargement ratios relative to a multiplicity of obstacles;
- means for enlarging widths of each of said identified wires based on the lowest upper limit of said wire width enlargement ratios relative to the respective obstacle;
- means for enlarging wire spacings between said identified wires based on the lowest upper limit of wire spacing enlargement ratios relative to respective obstacle;
- and
- means for adding the enlarged wire widths and the enlarged wire spacings to determine said enlarged region about said one obstacle.
A computer program product for transforming a topological wire route to a physical wire route on a printed circuit board, said program product comprising:
- a computer readable storage medium;
- first program instruction means for instructing a processor to select a topological wire;
- second program instruction means for instructing a processor to identify obstacles on both sides of said topological wire which sight selected topological wire;
- third program instruction means for instructing a processor to determine a region about each of the identified obstacles;
- and
- fourth program instruction means for instructing a processor to determine a route of a physical wire between said obstacles without passing through said regions, said physical wire, corresponding to said selected topological wire;
- and
- wherein all of said program instruction means are recorded on said storage medium.
A computer program product for transforming a topological wire route to a physical wire route on a printed circuit board, said program product comprising:
- a computer readable storage medium;
- a first program instruction means for instructing a processor to specify a first factor by which surplus space on said printed circuit board is allocated to enlargement of wire width and a second factor by which the surplus space is allocated to enlargement of wire spacing;
- a second program instruction means for instructing a processor to identify wires which cross a critical cut between one obstacle and another obstacle and lie between an identified topological wire and said one obstacle;
- a third program instruction means for instructing a processor to determine for each of said identified wires a multiplicity of upper limits of wire width enlargement ratios and wire spacing enlargement ratios relative to a multiplicity of obstacles;
- a fourth program instruction means for instructing a processor to enlarge widths of each of said identified wires based on the lowest upper limit of wire width enlargement ratios relative to the respective obstacle;
- a fifth program instruction means for instructing a processor to enlarge each of said wire spacings between said identified based on the lowest upper limit of wire spacing enlargement ratios relative to the respective obstacle;
- and
- a sixth program instruction means for instructing a processor to add the enlarged wire widths and the enlarged wire spacings to determine said enlarged region about said one obstacle;
- and wherein all of said program instruction means are recorded on said storage medium.
Dependencies are inferred from the claim text.