Semiconductor memory device having reduced data access time and improve speed
AssigneeHyundai Electronics Industries Co., Ltd.
InventorHa Ryong Yoon
Life of this patent
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Abstract
Disclosed is a semiconductor memory device comprising a precharging unit between bit lines within a memory cell region and bit lines within a sense amplifier region, respectively. When performing a column operation on the bit lines within the sense amplifier region upon consecutive read operations, the bit lines within the memory cell region are precharged and a wordline is disabled, and thus the memory cell region comes to the ready to enable a new wordline. Accordingly, the timing of row and column operations can be reduced, thereby reducing a data access time and realizing a high speed operation.
Claims9
In a semiconductor memory device comprising:
- a unit memory cell;
- a first line connecting means responsive to a first bit line separating signal for connecting or disconnecting bit lines within the unit memory cell region and bit lines within a sense amplifier region;
- a second line connecting means responsive to a second bit line separating signal for connecting or disconnecting bit lines within an other unit memory cell region and bit lines within the sense amplifier region;
- a first precharging means for equalizing and precharging the bit lines within the sense amplifier region under a control by a first precharging control signal;
- a bit line sense amplifier connected between the bit lines within the sense amplifier region for performing a bit line sensing operation under a control by sense amplifier control signals;
- and
- a data bus line connecting means responsive to a column selecting signal for connecting or disconnecting the bit lines within the sense amplifier region and data bus lines being characterized in that:
- said semiconductor memory device further includes a second precharging means for equalizing and precharging said bit lines within the unit memory cell region under a control by a second precharging control signal;
- wherein said first and second bit line separating signals are generated from a bit line separating signal generating means in accordance with a bank selecting signal and a sensing generating signal;
- said first bit line precharging control signal is generated from a first precharging control means in accordance with said bank selecting signal and said first and second bit line separating signals;
- and
- said second bit line precharging control signal is generated from a second precharging control means in accordance with said bank selecting signal and a /CAS signal.
Dependencies are inferred from the claim text.