Series connected multi-stage linear FET amplifier circuit

Abstract

A sampling circuit is arranged so that source voltages VDD and VEE, which are to be applied to two inverters at the latter stages in a signal path on the p-channel transistor side, are shifted to the positive side with respect to source voltages VCC and VSS that are applied to the other inverters. With such a power supply construction, video signals on the low-potential side in a video signal line are picked up by the n-channel transistor and video signals on the high-potential side are picked up by the p-channel transistor, and the resulting signals are supplied to a data signal line. This arrangement makes it possible to reduce the gate input voltage upon conduction of the sampling switch. Moreover, by shifting the levels of the source voltages as described above, it becomes possible to ensure writing and holding operations even in the case of having signals with a small amplitude. Therefore, even in the case when devices having low withstand voltage are used, no damage is caused on the circuit characteristics.

Dependencies are inferred from the claim text.