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US 6,225,689 B1Granted
Low profile multi-IC chip package connector
AssigneeMicron Technology, Inc.
InventorsWalter L. Moden, Jerrold L. King, Jerry M. Brooks
Life of this patent
Estimating the term…
Abstract
A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.
Claims64
A multi-chip semiconductor device package, comprising:
- a substrate having at least one circuit thereon;
- a plurality of encapsulated semiconductor devices, each device having an upper surface, a lower surface, a first lateral edge located between the upper surface and the lower surface, a second lateral edge located between the upper surface and the lower surface, and a plurality of outer leads extending from one of the first lateral edge and the second lateral edge;
- a cage for partially enclosing and retaining said plurality of semiconductor devices in a stack, said cage having at least one wall located adjacent a semiconductor device of said stacked plurality of semiconductor devices, said cage including:
- a flexible member generally perpendicular to the upper surface and the lower surface of said semiconductor device of said stacked plurality of semiconductor devices, said flexible member comprising a layer of material on an inner surface of a portion of said cage, a flexible member overlying said layer of material attached thereto, and at least one node on an interior of the at least one cage wall adjacent a semiconductor device of said stacked plurality of encapsulated integrated circuit devices retaining at least one semiconductor device of said stacked plurality of semiconductor devices in said cage, said at least one node comprising a removable polymeric adhesive attaching a semiconductor device of said stacked plurality of semiconductor devices to said cage;
- and
- a conductive bus line formed on said flexible member, said bus line generally substantially perpendicular to said upper surface and lower surface of said stacked plurality of semiconductor devices contacting an equivalent lead of said plurality of outer leads of each device of said stacked plurality of semiconductor devices and connected to said at least one circuit of said substrate.
3 more elements
A high-speed multi-chip semiconductor device package, comprising:
- a substrate having a plurality of circuits thereon;
- a stacked plurality of packaged encapsulated semiconductor devices, each package having an upper major surface and a lower major surface having lateral edges therebetween and a plurality of outer leads extending from at least one lateral edge of the lateral edges;
- a cage of connected members for partially enclosing and retaining said stacked plurality of packages encapsulated semiconductor devices in a stack, said cage including:
- a layer of material on an inner surface of one of said connected members, a flexible member overlying said layer of material attached thereto, and at least one node on an interior of a connected member adjacent a packaged semiconductor device of said stacked plurality of encapsulated semiconductor devices retaining said package in said cage, said at least one node comprising a rib substantially parallel to a major surface of a packaged encapsulated semiconductor device of said stacked plurality of encapsulated semiconductor devices, said rib comprising a removable polymeric adhesive attaching a package to said cage;
- and
- a conductive bus line formed on said flexible member, said bus line generally perpendicular to said opposed upper and lower major surfaces of said stacked plurality of packaged encapsulated semiconductor devices contacting with said plurality of outer leads of each of said stacked plurality of packaged encapsulated semiconductor devices connected to a circuit of said plurality of circuits of said substrate.
3 more elements
A high-speed multi-chip package, comprising:
- a substrate having a plurality of circuits thereon;
- a stacked plurality of packaged encapsulated semiconductor devices, each packaged semiconductor device having opposed major upper and lower surfaces having lateral edges therebetween and a plurality of outer leads extending from at least one lateral edge of the lateral edges;
- a cage of connected members partially enclosing and retaining said plurality of stacked semiconductor devices in a stack;
- a flexible member generally perpendicular to said opposed major upper and lower surfaces, said flexible member comprising a layer of material on an inner surface of one of said flexible members and a flexible member overlying said layer of material attached thereto;
- a conductive bus line formed on said flexible member, said bus line generally perpendicular to said opposed major upper and lower surfaces of said plurality of stacked semiconductor device packages contacting said plurality of outer leads of each of said plurality of stacked semiconductor device packages and connected to a circuit of said plurality of circuits of said substrate;
- and
- at least one node on an interior wall of said cage adjacent a package of said plurality of stacked semiconductor device packages retaining said package in said cage, said at least one node comprising a rib substantially parallel to a major surface of said major upper and lower surfaces of said package, said rib comprising a removable polymeric adhesive fixing said package to said cage.
4 more elements
A high-speed multi-chip package, comprising:
- a substrate having a plurality of circuits thereon;
- a stacked plurality of packaged encapsulated semiconductor device packages, each package having opposed major upper and lower surfaces having lateral edges therebetween and a plurality of outer leads extending from at least one lateral edge of said lateral edges;
- a cage of connected members for partially enclosing and retaining said plurality of semiconductor device packages in a stack;
- a flexible member generally perpendicular to said opposed major upper and lower surfaces, said flexible member comprising a layer of material on an inner surface of one of said flexible members and a flexible member overlying said layer of material and attached thereto;
- a conductive bus line formed on said flexible member, said bus line generally perpendicular to said opposed major upper and lower surfaces of said plurality of semiconductor device packages contacting said plurality of outer leads of each of said plurality of semiconductor device packages connected to a circuit of said plurality of circuits of said substrate;
- and
- at least one node on an interior wall of said cage adjacent a package of said plurality of semiconductor device packages retaining said package in said cage, said at least one node comprising a rib substantially parallel to a major surface of said upper and lower surfaces of said package, said rib comprising a removable polymeric adhesive attaching said package to said cage.
4 more elements
Dependencies are inferred from the claim text.